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Message-ID: <YWf1eXjYOR5Su5Zn@myrica>
Date:   Thu, 14 Oct 2021 10:16:41 +0100
From:   Jean-Philippe Brucker <jean-philippe@...aro.org>
To:     "Tian, Kevin" <kevin.tian@...el.com>
Cc:     Jason Gunthorpe <jgg@...dia.com>,
        "kvm@...r.kernel.org" <kvm@...r.kernel.org>,
        "jasowang@...hat.com" <jasowang@...hat.com>,
        "kwankhede@...dia.com" <kwankhede@...dia.com>,
        "hch@....de" <hch@....de>, "Jiang, Dave" <dave.jiang@...el.com>,
        "Raj, Ashok" <ashok.raj@...el.com>,
        "corbet@....net" <corbet@....net>,
        "parav@...lanox.com" <parav@...lanox.com>,
        Alex Williamson <alex.williamson@...hat.com>,
        "lkml@...ux.net" <lkml@...ux.net>,
        "david@...son.dropbear.id.au" <david@...son.dropbear.id.au>,
        "dwmw2@...radead.org" <dwmw2@...radead.org>,
        "Tian, Jun J" <jun.j.tian@...el.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "lushenming@...wei.com" <lushenming@...wei.com>,
        "pbonzini@...hat.com" <pbonzini@...hat.com>,
        "robin.murphy@....com" <robin.murphy@....com>
Subject: Re: [RFC 10/20] iommu/iommufd: Add IOMMU_DEVICE_GET_INFO

On Thu, Oct 14, 2021 at 08:01:49AM +0000, Tian, Kevin wrote:
> > From: Jean-Philippe Brucker <jean-philippe@...aro.org>
> > Sent: Thursday, September 30, 2021 6:33 PM
> > 
> > The PTE flags define whether the memory access is cache-coherent or not.
> > * WB is cacheable (short for write-back cacheable. Doesn't matter here
> >   what OI or RWA mean.)
> > * NC is non-cacheable.
> > 
> >          | Normal PCI access | No_snoop PCI access
> >   -------+-------------------+-------------------
> >   PTE WB | Cacheable         | Non-cacheable
> >   PTE NC | Non-cacheable     | Non-cacheable
> 
> This implies that PCI no-snoop supersedes PTE flags when it's supported
> by the system?
> 

Yes, no way for the SMMU to ignore no-snoop, as far as I can see

Thanks,
Jean

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