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Message-ID: <641e8b18-230d-699c-6ec5-1aa107d7d5bb@linux.intel.com>
Date: Thu, 14 Oct 2021 06:47:14 -0700
From: Andi Kleen <ak@...ux.intel.com>
To: Thomas Gleixner <tglx@...utronix.de>,
Kuppuswamy Sathyanarayanan
<sathyanarayanan.kuppuswamy@...ux.intel.com>,
Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
x86@...nel.org, Paolo Bonzini <pbonzini@...hat.com>,
David Hildenbrand <david@...hat.com>,
Andrea Arcangeli <aarcange@...hat.com>,
Josh Poimboeuf <jpoimboe@...hat.com>,
Juergen Gross <jgross@...e.com>, Deep Shah <sdeep@...are.com>,
VMware Inc <pv-drivers@...are.com>,
Vitaly Kuznetsov <vkuznets@...hat.com>,
Wanpeng Li <wanpengli@...cent.com>,
Jim Mattson <jmattson@...gle.com>,
Joerg Roedel <joro@...tes.org>
Cc: Peter H Anvin <hpa@...or.com>, Dave Hansen <dave.hansen@...el.com>,
Tony Luck <tony.luck@...el.com>,
Dan Williams <dan.j.williams@...el.com>,
Kirill Shutemov <kirill.shutemov@...ux.intel.com>,
Sean Christopherson <seanjc@...gle.com>,
Kuppuswamy Sathyanarayanan <knsathya@...nel.org>,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v10 10/11] x86/tdx: Don't write CSTAR MSR on Intel
>> - wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat);
>> + /*
>> + * CSTAR is not needed on Intel because it doesn't support
>> + * 32bit SYSCALL, but only SYSENTER. On a TDX guest
>> + * it leads to a #GP.
> Sigh. Above you write it raises #VE, but now it's #GP !?!
The unhandled #VE trap is handled like a #GP, which is then caught by
the kernel wrmsr code.
So both are correct.
>
> Intel CPUs do not support 32-bit SYSCALL. Writing to MSR_CSTAR
> is normaly ignored by the CPU, but raises a #VE trap in a TDX
> guest.
>
> Hmm?
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