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Message-ID: <4090acf8-c8af-d98c-2121-9fd105365e55@gmail.com>
Date: Fri, 15 Oct 2021 03:43:49 +0300
From: Dmitry Osipenko <digetx@...il.com>
To: Stephen Boyd <sboyd@...nel.org>,
Adrian Hunter <adrian.hunter@...el.com>,
Jonathan Hunter <jonathanh@...dia.com>,
Lee Jones <lee.jones@...aro.org>,
Michael Turquette <mturquette@...libre.com>,
Mikko Perttunen <mperttunen@...dia.com>,
Nishanth Menon <nm@...com>, Peter Chen <peter.chen@...nel.org>,
Peter De Schrijver <pdeschrijver@...dia.com>,
Rob Herring <robh+dt@...nel.org>,
Thierry Reding <thierry.reding@...il.com>,
Ulf Hansson <ulf.hansson@...aro.org>,
Uwe Kleine-König <u.kleine-koenig@...gutronix.de>,
Viresh Kumar <vireshk@...nel.org>
Cc: linux-kernel@...r.kernel.org, linux-tegra@...r.kernel.org,
linux-pm@...r.kernel.org, linux-usb@...r.kernel.org,
linux-staging@...ts.linux.dev, linux-pwm@...r.kernel.org,
linux-mmc@...r.kernel.org, dri-devel@...ts.freedesktop.org,
devicetree@...r.kernel.org, linux-clk@...r.kernel.org,
Mark Brown <broonie@...nel.org>,
Vignesh Raghavendra <vigneshr@...com>,
Richard Weinberger <richard@....at>,
Miquel Raynal <miquel.raynal@...tlin.com>,
Lucas Stach <dev@...xeye.de>, Stefan Agner <stefan@...er.ch>,
Mauro Carvalho Chehab <mchehab@...nel.org>,
David Heidelberg <david@...t.cz>
Subject: Re: [PATCH v12 05/35] dt-bindings: clock: tegra-car: Document new
clock sub-nodes
15.10.2021 03:16, Stephen Boyd пишет:
> Quoting Dmitry Osipenko (2021-09-20 11:11:15)
>> diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml
>> index 459d2a525393..f832abb7f11a 100644
>> --- a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml
>> +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml
>> @@ -42,6 +42,36 @@ properties:
>> "#reset-cells":
>> const: 1
>>
>> +patternProperties:
>> + "^(sclk)|(pll-[cem])$":
>> + type: object
>> + properties:
>> + compatible:
>> + enum:
>> + - nvidia,tegra20-sclk
>> + - nvidia,tegra30-sclk
>> + - nvidia,tegra30-pllc
>> + - nvidia,tegra30-plle
>> + - nvidia,tegra30-pllm
>> +
>> + operating-points-v2: true
>> +
>> + clocks:
>> + items:
>> + - description: node's clock
>> +
>> + power-domains:
>> + maxItems: 1
>> + description: phandle to the core SoC power domain
>
> Is this done to associate the power domain with a particular clk? And an
> OPP table with a particular clk?
Yes
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