linux-kernel - Re: [PATCH v1] PCI: qcom: Fix incorrect register offset in pcie init

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20211015135755.GA2098274@bhelgaas>
Date:   Fri, 15 Oct 2021 08:57:55 -0500
From:   Bjorn Helgaas <helgaas@...nel.org>
To:     Prasad Malisetty <pmaliset@...eaurora.org>
Cc:     svarbanov@...sol.com, agross@...nel.org,
        bjorn.andersson@...aro.org, lorenzo.pieralisi@....com,
        linux-arm-msm@...r.kernel.org, linux-pci@...r.kernel.org,
        linux-kernel@...r.kernel.org, vbadigan@...eaurora.org,
        kw@...ux.com, bhelgaas@...gle.com, manivannan.sadhasivam@...aro.org
Subject: Re: [PATCH v1] PCI: qcom: Fix incorrect register offset in pcie init

This looks specific to SDM845, so the subject line should mention
SDM845, e.g.,

  PCI: qcom: Fix SDM845 incorrect register offset

On Fri, Oct 15, 2021 at 12:28:49AM +0530, Prasad Malisetty wrote:
> In pcie_init_2_7_0 one of the register writes using incorrect offset
> as per the platform register definitions (PCIE_PARF_AXI_MSTR_WR_ADDR_HALT
> offset value should be 0x1A8 instead 0x178).
> Update the correct offset value for SDM845 platform.

Add "()" after function name.  Add blank line between paragraphs.

It'd be nice to have a clue about what fails because of the incorrect
register offset.  ed8cc3b1fc84 is almost two years old, so I guess
it's not an obvious issue.

> fixes: ed8cc3b1 ("PCI: qcom: Add support for SDM845 PCIe controller")

Capitalize "Fixes:", use 12-char SHA1, remove blank line after.  Look
at previous git history and copy the style there.

> 
> Signed-off-by: Prasad Malisetty <pmaliset@...eaurora.org>

It looks like ed8cc3b1fc84 appeared in v5.6, so this should probably
have a "Cc: stable@...r.kernel.org" tag as well.

> ---
>  drivers/pci/controller/dwc/pcie-qcom.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 8a7a300..5bce152 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -1230,9 +1230,9 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
>  	writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
>  
>  	if (IS_ENABLED(CONFIG_PCI_MSI)) {
> -		val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
> +		val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
>  		val |= BIT(31);
> -		writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
> +		writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
>  	}
>  
>  	return 0;
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>