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Date:   Mon, 18 Oct 2021 04:37:49 +0000
From:   Bhaskara Budiredla <bbudiredla@...vell.com>
To:     Bharat Bhushan <bbhushan2@...vell.com>,
        "will@...nel.org" <will@...nel.org>,
        "mark.rutland@....com" <mark.rutland@....com>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        Sunil Kovvuri Goutham <sgoutham@...vell.com>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
CC:     Bharat Bhushan <bbhushan2@...vell.com>
Subject: RE: [PATCH v5 3/4] perf/marvell: cn10k DDR perfmon event overflow
 handling

>Two fixed event counters starts counting from zero on overflow, so overflow
>condition is when new count less than previous count. While eight
>programmable event counters freezes at maximum value. Also individual
>counter cannot be restarted, so need to restart all eight counters.
>
>Signed-off-by: Bharat Bhushan <bbhushan2@...vell.com>
>---

Reviewed-by: Bhaskara Budiredla <bbudiredla@...vell.com>

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