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Message-ID: <CY4PR1801MB207092F0F2EFABA1C8A5B1B4DEBC9@CY4PR1801MB2070.namprd18.prod.outlook.com>
Date: Mon, 18 Oct 2021 04:37:58 +0000
From: Bhaskara Budiredla <bbudiredla@...vell.com>
To: Bharat Bhushan <bbhushan2@...vell.com>,
"will@...nel.org" <will@...nel.org>,
"mark.rutland@....com" <mark.rutland@....com>,
"robh+dt@...nel.org" <robh+dt@...nel.org>,
Sunil Kovvuri Goutham <sgoutham@...vell.com>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
CC: Bharat Bhushan <bbhushan2@...vell.com>
Subject: RE: [PATCH v5 4/4] perf/marvell: cn10k DDR perf event core ownership
>
>As DDR perf event counters are not per core, so they should be accessed only
>by one core at a time. Select new core when previously owning core is going
>offline.
>
>Signed-off-by: Bharat Bhushan <bbhushan2@...vell.com>
>---
Reviewed-by: Bhaskara Budiredla <bbudiredla@...vell.com>
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