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Message-ID: <YXGD5OFbI7TEDFTr@hirez.programming.kicks-ass.net>
Date: Thu, 21 Oct 2021 17:14:44 +0200
From: Peter Zijlstra <peterz@...radead.org>
To: Arnd Bergmann <arnd@...db.de>
Cc: Will Deacon <will@...nel.org>, Boqun Feng <boqun.feng@...il.com>,
Ingo Molnar <mingo@...nel.org>,
Waiman Long <longman@...hat.com>,
linux-arch <linux-arch@...r.kernel.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
Guo Ren <guoren@...nel.org>,
Palmer Dabbelt <palmerdabbelt@...gle.com>,
Anup Patel <anup@...infault.org>,
linux-riscv <linux-riscv@...ts.infradead.org>,
Christoph Müllner <christophm30@...il.com>,
Stafford Horne <shorne@...il.com>
Subject: Re: [PATCH] locking: Generic ticket lock
On Thu, Oct 21, 2021 at 03:49:51PM +0200, Arnd Bergmann wrote:
> On Thu, Oct 21, 2021 at 3:05 PM Peter Zijlstra <peterz@...radead.org> wrote:
> >
> > Therefore provide ticket locks, which depend on a single atomic
> > operation (fetch_add) while still providing fairness.
>
> Nice!
>
> Aside from the qspinlock vs ticket-lock question, can you describe the
> tradeoffs between this generic ticket lock and a custom implementation
> in architecture code? Should we convert most architectures over
> to the generic code in the long run, or is there something they
> can usually do better with an inline asm based ticket lock
I think for a load-store arch this thing should generate pretty close to
optimal code. x86 can do ticket_unlock() slightly better using a single
INCW (or ADDW 1) on the owner subword, where this implementation will to
separate load-add-store instructions.
If that is actually measurable is something else entirely.
> or a trivial test-and-set?
If your SMP arch is halfway sane (no fwd progress issues etc..) then
ticket should behave well and avoid the starvation/variablilty of TaS
lock.
The big exception there is virtualized architectures, ticket is
absolutely horrendous for 'guests' (any fair lock is for that matter).
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