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Date: Sat, 23 Oct 2021 19:13:58 +0800
From: Flora Fu <flora.fu@...iatek.com>
To: Matthias Brugger <matthias.bgg@...il.com>,
Mark Brown <broonie@...nel.org>,
Sumit Semwal <sumit.semwal@...aro.org>
CC: <linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-mediatek@...ts.infradead.org>,
<linux-media@...r.kernel.org>, <dri-devel@...ts.freedesktop.org>,
<linaro-mm-sig@...ts.linaro.org>, Flora Fu <flora.fu@...iatek.com>,
Yong Wu <yong.wu@...iatek.com>,
Pi-Cheng Chen <pi-cheng.chen@...iatek.com>
Subject: [RFC 02/13] dt-bindings: soc: mediatek: apusys: Add new document for APU power
Add new document for APU power controller.
Signed-off-by: Flora Fu <flora.fu@...iatek.com>
---
.../soc/mediatek/mediatek,apu-pwr.yaml | 88 +++++++++++++++++++
1 file changed, 88 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pwr.yaml
diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pwr.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pwr.yaml
new file mode 100644
index 000000000000..0fd5af5138e3
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pwr.yaml
@@ -0,0 +1,88 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# # Copyright 2021 MediaTek Inc.
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/soc/mediatek/mediatek,apu-pwr.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Mediatek APU Power
+
+description: |
+ Mediatek AI Process Unit (APU) power driver support for subsys clock and
+ regulator controller. It will has device link to iommu-apu and apusys-rv
+ tinysys driver to ensure the power state is ready for hardware
+ in sub modules.
+
+maintainers:
+ - Flora Fu <flora.fu@...iatek.com>
+
+properties:
+ compatible:
+ oneOf:
+ - const: mediatek,apusys-power
+ - items:
+ - const: mediatek,apusys-power
+ - const: mediatek,mt8192-apu-power
+
+ reg:
+ minItems: 1
+
+ reg-names:
+ minItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ vvpu-supply:
+ description: apu vpu regulator supply.
+
+ vmdla-supply:
+ description: apu mdla regulator supply.
+
+ clocks:
+ description: Contains module clock source and clock names
+
+ clock-names:
+ description: Names of the clocks list in clocks property
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - vvpu-supply
+ - vmdla-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8192-clk.h>
+ apusys_power: apusys_power@...f1000 {
+ compatible = "mediatek,apusys-power",
+ "mediatek,mt8192-apu-power";
+ reg = <0x190f1000 0x1000>;
+ reg-names = "apu_pcu";
+ power-domains = <&apuspm 0>;
+ vvpu-supply = <&mt6359_vproc1_buck_reg>;
+ vmdla-supply = <&mt6359_vproc2_buck_reg>;
+ clocks = <&topckgen CLK_TOP_DSP_SEL>,
+ <&topckgen CLK_TOP_DSP1_SEL>,
+ <&topckgen CLK_TOP_DSP1_NPUPLL_SEL>,
+ <&topckgen CLK_TOP_DSP2_SEL>,
+ <&topckgen CLK_TOP_DSP2_NPUPLL_SEL>,
+ <&topckgen CLK_TOP_DSP5_SEL>,
+ <&topckgen CLK_TOP_DSP5_APUPLL_SEL>,
+ <&topckgen CLK_TOP_IPU_IF_SEL>,
+ <&clk26m>;
+ clock-names = "clk_top_dsp_sel",
+ "clk_top_dsp1_sel",
+ "clk_top_dsp1_npupll_sel",
+ "clk_top_dsp2_sel",
+ "clk_top_dsp2_npupll_sel",
+ "clk_top_dsp5_sel",
+ "clk_top_dsp5_apupll_sel",
+ "clk_top_ipu_if_sel",
+ "clk_top_clk26m";
+ };
--
2.18.0
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