linux-kernel - Re: [v1] drm/msm/disp/dpu1: set default group ID for CTL.

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Message-ID: <CAE-0n51QgYprv+BPKWHSVgUFDhHzb0t=DRBG_g9yvXeMWyaVqg@mail.gmail.com>
Date:   Thu, 28 Oct 2021 15:19:59 -0700
From:   Stephen Boyd <swboyd@...omium.org>
To:     Kalyan Thota <quic_kalyant@...cinc.com>,
        devicetree@...r.kernel.org, dri-devel@...ts.freedesktop.org,
        freedreno@...ts.freedesktop.org, linux-arm-msm@...r.kernel.org,
        y@...lcomm.com
Cc:     Kalyan Thota <kalyan_t@...eaurora.org>,
        linux-kernel@...r.kernel.org, robdclark@...il.com,
        dianders@...omium.org, mkrishn@...eaurora.org,
        abhinavk@...eaurora.org
Subject: Re: [v1] drm/msm/disp/dpu1: set default group ID for CTL.

Quoting Kalyan Thota (2021-10-28 07:05:01)
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 4ade44b..57b9be1 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -179,13 +179,16 @@ enum {
>
>  /**
>   * CTL sub-blocks
> - * @DPU_CTL_SPLIT_DISPLAY       CTL supports video mode split display
> + * @DPU_CTL_SPLIT_DISPLAY,     CTL supports video mode split display
> + * @DPU_CTL_FETCH_ACTIVE,      Active CTL for fetch HW (SSPPs).
> + * @DPU_CTL_VM_CFG,            CTL supports multiple VMs.

Are those commas supposed to be colons? Also the application of the
period/full-stop is not consistent. Please pick one. I see the double
star so it looks like kernel-doc, but probably doesn't parse properly.

>   * @DPU_CTL_MAX
>   */
>  enum {
>         DPU_CTL_SPLIT_DISPLAY = 0x1,
>         DPU_CTL_ACTIVE_CFG,
>         DPU_CTL_FETCH_ACTIVE,
> +       DPU_CTL_VM_CFG,
>         DPU_CTL_MAX
>  };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> index 64740ddb..455b06a 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> @@ -498,6 +498,9 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
>         u32 intf_active = 0;
>         u32 mode_sel = 0;
>

Can we get a comment here about what's happening?

> +       if ((test_bit(DPU_CTL_VM_CFG, &ctx->caps->features)))

Does it need to be atomic? Sort of doubt it, so probably __test_bit()
would work just as well.

> +               mode_sel = 0xf0000000;

How about a define for 0xf0000000? Preferably a name that matches the
register description for this bit pattern.

> +
>         if (cfg->intf_mode_sel == DPU_CTL_MODE_SEL_CMD)
>                 mode_sel |= BIT(17);
>