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Message-ID: <a6ed700a76a03eefceca0ce735ab6fd3cab19841.camel@linux.intel.com>
Date: Thu, 04 Nov 2021 07:15:42 -0700
From: Srinivas Pandruvada <srinivas.pandruvada@...ux.intel.com>
To: Steven Rostedt <rostedt@...dmis.org>
Cc: rafael@...nel.org, viresh.kumar@...aro.org,
linux-pm@...r.kernel.org, linux-kernel@...r.kernel.org,
torvalds@...ux-foundation.org, lenb@...nel.org
Subject: Re: [PATCH] cpufreq: intel_pstate: Fix unchecked MSR 0x773 access
On Thu, 2021-11-04 at 09:30 -0400, Steven Rostedt wrote:
> On Wed, 3 Nov 2021 22:19:25 -0700
> Srinivas Pandruvada <srinivas.pandruvada@...ux.intel.com> wrote:
>
> > It is possible that on some platforms HWP interrupts are disabled.
> > In
> > that case accessing MSR 0x773 will result in warning.
> >
> > So check X86_FEATURE_HWP_NOTIFY feature to access MSR 0x773. The
> > other
> > places in code where this MSR is accessed, already checks this
> > feature
> > except during disable path called during cpufreq offline and
> > suspend
> > callbacks.
> >
> > Fixes: 57577c996d73 ("cpufreq: intel_pstate: Process HWP Guaranteed
> > change notification")
> > Reported-by: Steven Rostedt <rostedt@...dmis.org>
>
> I added this patch on top of the above commit and I verified that the
> issue
> goes away. And just to confirm, I removed the patch, and the issue
> reappeared.
>
> Tested-by: Steven Rostedt (VMware) <rostedt@...dmis.org>
>
Thanks for the test.
Sorry again for the mess up.
-Srinivas
> -- Steve
>
>
> > Signed-off-by: Srinivas Pandruvada <
> > srinivas.pandruvada@...ux.intel.com>
> > ---
> > drivers/cpufreq/intel_pstate.c | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/drivers/cpufreq/intel_pstate.c
> > b/drivers/cpufreq/intel_pstate.c
> > index 349ddbaef796..1e6898dc76b6 100644
> > --- a/drivers/cpufreq/intel_pstate.c
> > +++ b/drivers/cpufreq/intel_pstate.c
> > @@ -1620,6 +1620,9 @@ static void
> > intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata)
> > {
> > unsigned long flags;
> >
> > + if (!boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
> > + return;
> > +
> > /* wrmsrl_on_cpu has to be outside spinlock as this can
> > result in IPC */
> > wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
> >
>
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