linux-kernel - Re: [PATCH v3 01/21] x86/cpufreatures: add AMD Collaborative Processor Performance Control feature flag

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Message-ID: <YYZY5koNqNZD/Fio@zn.tnic>
Date:   Sat, 6 Nov 2021 11:28:54 +0100
From:   Borislav Petkov <bp@...e.de>
To:     Huang Rui <ray.huang@....com>
Cc:     "Rafael J . Wysocki" <rafael.j.wysocki@...el.com>,
        Viresh Kumar <viresh.kumar@...aro.org>,
        Shuah Khan <skhan@...uxfoundation.org>,
        Peter Zijlstra <peterz@...radead.org>,
        Ingo Molnar <mingo@...nel.org>,
        Giovanni Gherdovich <ggherdovich@...e.cz>,
        linux-pm@...r.kernel.org, Deepak Sharma <deepak.sharma@....com>,
        Alex Deucher <alexander.deucher@....com>,
        Mario Limonciello <mario.limonciello@....com>,
        Steven Noonan <steven@...vesoftware.com>,
        Nathan Fontenot <nathan.fontenot@....com>,
        Jinzhou Su <Jinzhou.Su@....com>,
        Xiaojian Du <Xiaojian.Du@....com>,
        linux-kernel@...r.kernel.org, x86@...nel.org
Subject: Re: [PATCH v3 01/21] x86/cpufreatures: add AMD Collaborative
 Processor Performance Control feature flag

On Fri, Oct 29, 2021 at 09:02:21PM +0800, Huang Rui wrote:
> Add Collaborative Processor Performance Control feature flag for AMD
> processors.
> 
> This feature flag will be used on the following amd-pstate driver. The
> amd-pstate driver has two approaches to implement the frequency control
> behavior. That depends on the CPU hardware implementation. One is "Full
> MSR Support" and another is "Shared Memory Support". The feature flag
> indicates the current processors with "Full MSR Support".
> 
> Signed-off-by: Huang Rui <ray.huang@....com>
> ---
>  arch/x86/include/asm/cpufeatures.h | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index d0ce5cfd3ac1..f23dc1abd485 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -313,6 +313,7 @@
>  #define X86_FEATURE_AMD_SSBD		(13*32+24) /* "" Speculative Store Bypass Disable */
>  #define X86_FEATURE_VIRT_SSBD		(13*32+25) /* Virtualized Speculative Store Bypass Disable */
>  #define X86_FEATURE_AMD_SSB_NO		(13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */
> +#define X86_FEATURE_AMD_CPPC		(13*32+27) /* Collaborative Processor Performance Control */

I know I have acked this already but an Intel patchset made me look at
this again: there's no need to have the vendor name in the feature name:

X86_FEATURE_CPPC

is perfectly fine.

-- 
Regards/Gruss,
    Boris.

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