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Message-ID: <CAL_JsqLQWYNHRyNNNeP5VvWJXxp1mmeMvz1DA3ZdyyqZkKzG3A@mail.gmail.com>
Date:   Mon, 15 Nov 2021 10:57:34 -0600
From:   Rob Herring <robh@...nel.org>
To:     Will Deacon <will@...nel.org>, Mark Rutland <mark.rutland@....com>,
        Peter Zijlstra <peterz@...radead.org>
Cc:     Jonathan Corbet <corbet@....net>,
        Catalin Marinas <catalin.marinas@....com>,
        Ingo Molnar <mingo@...hat.com>,
        Arnaldo Carvalho de Melo <acme@...nel.org>,
        Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
        Jiri Olsa <jolsa@...hat.com>,
        Namhyung Kim <namhyung@...nel.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Borislav Petkov <bp@...en8.de>, X86 ML <x86@...nel.org>,
        "H. Peter Anvin" <hpa@...or.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
        linux-perf-users@...r.kernel.org
Subject: Re: [PATCH v12 0/5] Another version of arm64 userspace counter access support.

On Wed, Oct 27, 2021 at 3:16 PM Rob Herring <robh@...nel.org> wrote:
>
> The arm64 support departs from the x86 implementation by requiring the user
> to explicitly request user access (via attr.config1) and only enables access
> for task bound events. Since usage is explicitly requested, access is
> enabled at perf_event_open() rather than on mmap() as that greatly
> simplifies the implementation. Rather than trying to lock down the access
> as the x86 implementation has been doing, we can start with only a limited
> use case enabled and later expand it if needed.
>
> I've run this version thru Vince's perf tests[14] with arm64 support added.
> I wish I'd found these tests sooner...
>
> This originally resurrected Raphael's series[1] to enable userspace counter
> access on arm64. My previous versions are here
> [2][3][4][5][6][7][8][9][10][11][12].
> A git branch is here[13].
>
> Changes in v12:
>  - Zero PMSELR_EL0 when userspace access is enabled
>  - Return -EOPNOTSUPP for if h/w doesn't support 64-bit counters

Will, the series rebases cleanly on v5.16-rc1. Please let me know if
you want me to resend.

Peter, Will is waiting on an ack on the core/x86 bits from you.

Rob

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