linux-kernel - Re: [PATCH v4 3/6] clk: qcom: Add SDX65 GCC support

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Message-ID: <YZNsvjwp0/AX0Hdo@matsya>
Date:   Tue, 16 Nov 2021 14:03:02 +0530
From:   Vinod Koul <vkoul@...nel.org>
To:     quic_vamslank@...cinc.com
Cc:     agross@...nel.org, bjorn.andersson@...aro.org,
        mturquette@...libre.com, sboyd@...nel.org, robh+dt@...nel.org,
        tglx@...utronix.de, maz@...nel.org, linux-arm-msm@...r.kernel.org,
        linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
        devicetree@...r.kernel.org, manivannan.sadhasivam@...aro.org,
        kernel test robot <lkp@...el.com>
Subject: Re: [PATCH v4 3/6] clk: qcom: Add SDX65 GCC support

On 15-11-21, 23:38, quic_vamslank@...cinc.com wrote:
> From: Vamsi Krishna Lanka <quic_vamslank@...cinc.com>
> 
> Add Global Clock Controller (GCC) support for SDX65 SoCs from Qualcomm.
> 
> Signed-off-by: Vamsi Krishna Lanka <quic_vamslank@...cinc.com>
> Reported-by: kernel test robot <lkp@...el.com>

Missing support reported ??

> +static struct clk_branch gcc_ahb_pcie_link_clk = {
> +	.halt_reg = 0x2e004,
> +	.halt_check = BRANCH_HALT,
> +	.clkr = {
> +		.enable_reg = 0x2e004,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data){
> +			.name = "gcc_ahb_pcie_link_clk",
> +			.flags = CLK_IS_CRITICAL,
> +			.ops = &clk_branch2_ops,
> +		},

If this clk is critical then why model in linux, enable directly in probe
and leave it...?

> +static struct clk_branch gcc_pcie_0_clkref_en = {
> +	.halt_reg = 0x88004,
> +	.halt_check = BRANCH_HALT_DELAY,

Why delay, add a comment at least for that

> +	.clkr = {
> +		.enable_reg = 0x88004,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data){
> +			.name = "gcc_pcie_0_clkref_en",
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_pcie_aux_clk = {
> +	.halt_reg = 0x43034,
> +	.halt_check = BRANCH_HALT_DELAY,

Here too

> +static struct clk_branch gcc_pcie_mstr_axi_clk = {
> +	.halt_reg = 0x43024,
> +	.halt_check = BRANCH_HALT_VOTED,
> +	.hwcg_reg = 0x43024,
> +	.hwcg_bit = 1,
> +	.clkr = {
> +		.enable_reg = 0x6d010,
> +		.enable_mask = BIT(1),
> +		.hw.init = &(struct clk_init_data){
> +			.name = "gcc_pcie_mstr_axi_clk",
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_pcie_pipe_clk = {
> +	.halt_reg = 0x4303c,
> +	.halt_check = BRANCH_HALT_DELAY,

here as well and few more places I guess

> +static struct clk_branch gcc_xo_pcie_link_clk = {
> +	.halt_reg = 0x2e008,
> +	.halt_check = BRANCH_HALT,
> +	.hwcg_reg = 0x2e008,
> +	.hwcg_bit = 1,
> +	.clkr = {
> +		.enable_reg = 0x2e008,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data){
> +			.name = "gcc_xo_pcie_link_clk",
> +			.flags = CLK_IS_CRITICAL,

Here as well
-- 
~Vinod