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Message-ID: <YZOEM591s7iulPH1@smile.fi.intel.com>
Date: Tue, 16 Nov 2021 12:13:07 +0200
From: Andy Shevchenko <andy.shevchenko@...il.com>
To: Serge Semin <Sergey.Semin@...kalelectronics.ru>
Cc: Serge Semin <fancer.lancer@...il.com>,
Mark Brown <broonie@...nel.org>,
Nandhini Srikandan <nandhini.srikandan@...el.com>,
Andy Shevchenko <andy@...nel.org>, linux-spi@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 7/7] spi: dw: Define the capabilities in a continuous
bit-flags set
On Mon, Nov 15, 2021 at 09:19:17PM +0300, Serge Semin wrote:
> Since the DW_SPI_CAP_DWC_HSSI capability has just been replaced with using
> the DW SSI IP-core versions interface, the DW SPI capability flags are now
> represented with a gap. Let's fix it by redefining the DW_SPI_CAP_DFS32
> macro to setting BIT(2) of the capabilities field.
>
> Signed-off-by: Serge Semin <Sergey.Semin@...kalelectronics.ru>
> Suggested-by: Andy Shevchenko <andy.shevchenko@...il.com>
Fine with me, thanks!
Reviewed-by: Andy Shevchenko <andy.shevchenko@...il.com>
> ---
>
> Changelog v3:
> - This is a new patch unpinned from the previous one as of Andy
> suggested.
> ---
> drivers/spi/spi-dw.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
> index 8334e6b35f89..d5ee5130601e 100644
> --- a/drivers/spi/spi-dw.h
> +++ b/drivers/spi/spi-dw.h
> @@ -32,7 +32,7 @@
> /* DW SPI controller capabilities */
> #define DW_SPI_CAP_CS_OVERRIDE BIT(0)
> #define DW_SPI_CAP_KEEMBAY_MST BIT(1)
> -#define DW_SPI_CAP_DFS32 BIT(3)
> +#define DW_SPI_CAP_DFS32 BIT(2)
>
> /* Register offsets (Generic for both DWC APB SSI and DWC SSI IP-cores) */
> #define DW_SPI_CTRLR0 0x00
> --
> 2.33.0
>
--
With Best Regards,
Andy Shevchenko
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