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Date:   Mon, 15 Nov 2021 12:18:06 -0800
From:   "Andy Lutomirski" <luto@...nel.org>
To:     "Arjan van de Ven" <arjan@...ux.intel.com>,
        "Asit K Mallick" <asit.k.mallick@...el.com>,
        "Dave Hansen" <dave.hansen@...ux.intel.com>,
        "Brown, Len" <len.brown@...el.com>,
        "Thomas Gleixner" <tglx@...utronix.de>,
        "Peter Zijlstra (Intel)" <peterz@...radead.org>,
        "the arch/x86 maintainers" <x86@...nel.org>,
        "Borislav Petkov" <bp@...en8.de>,
        "Linux Kernel Mailing List" <linux-kernel@...r.kernel.org>,
        "Bae, Chang Seok" <chang.seok.bae@...el.com>
Cc:     "Andrew Cooper" <andrew.cooper3@...rix.com>
Subject: Re: Revisiting XFD-based AMX and heterogenous systems



On Mon, Nov 15, 2021, at 12:11 PM, Arjan van de Ven wrote:
> On 11/15/2021 11:59 AM, Andy Lutomirski wrote:
>> [resend -- first try was HTML.  oops.]
>> 
>> Hi all-
>> 
>> I just learned that current Alder Lake review samples are actually heterogenous, at least physically.  The performance cores have AVX-512 and the efficiency cores don't have AVX-512.  Since no OS supports actual runtime ISA heterogeneity, this feature seems to be hidden in that one must choose, per boot, whether one wants AVX-512 or efficiency cores, but the CPU is physically heterogenous.
>> 
>> All the earlier discussions about Linux AMX architecture happened under the assumption that xfeature-heterogenous systems would never happen, and my grudging acceptance of the XFD model was predicated on that.  But now we have obviously heterogenous hardware that is apparently actually shipping at least to reviewers, and I think we should revisit this before we merge AMX support.
>> 
>
> Alderlake is not heterogenous.
> This is not just an "OS can deal with it" thing... it's throughout 
> everything from low lower power delivery through bios through ...

Sure, but I bet the demand will be there.  The desktop gamer types will flip off E cores and flip on AVX512 and call it a day.  But the ones who want battery life will be annoyed, and I bet someone at Intel is contemplating how to switch it at runtime.

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