linux-kernel - Re: [PATCH 0/2] clk: samsung: exynos850: Implement CMU

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Message-ID: <CAPLW+4nphz7WEVAFye4tZNsYC3XqVGNCpVACCF6UAKXoUFthJQ@mail.gmail.com>
Date:   Thu, 18 Nov 2021 21:55:30 +0200
From:   Sam Protsenko <semen.protsenko@...aro.org>
To:     Sylwester Nawrocki <s.nawrocki@...sung.com>
Cc:     Sumit Semwal <sumit.semwal@...aro.org>, devicetree@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org,
        Paweł Chmiel <pawel.mikolaj.chmiel@...il.com>,
        linux-clk@...r.kernel.org, Tomasz Figa <tomasz.figa@...il.com>,
        Rob Herring <robh+dt@...nel.org>,
        Stephen Boyd <sboyd@...nel.org>, linux-kernel@...r.kernel.org,
        linux-samsung-soc@...r.kernel.org,
        Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>,
        Chanwoo Choi <cw00.choi@...sung.com>,
        Michael Turquette <mturquette@...libre.com>
Subject: Re: [PATCH 0/2] clk: samsung: exynos850: Implement CMU_CMGP

On Tue, 9 Nov 2021 at 18:44, Sam Protsenko <semen.protsenko@...aro.org> wrote:
>
> This series adds CMU_CMGP clock domain to Exynos850 clock driver. In
> particular it needs to enable HSI2C (High-Speed I2C) nodes. This series
> depends on CMU_APM series [1].
>
> Tested via /sys/kernel/debug/clk/clk_summary:
>
> <<<<<<<<<<<<<<<<<<<<<<<<<<<< cut here >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
>                                  enable  prepare  protect
>    clock                          count    count    count        rate
> ---------------------------------------------------------------------
>
> clk_rco_cmgp                         0        0        0    49152000
> oscclk                               1        1        0    26000000
>     mout_cmgp_adc                    0        0        0    26000000
> ...
>     gout_clkcmu_cmgp_bus             1        1        0   399750000
>        gout_cmgp_usi1_pclk           0        0        0   399750000
>        gout_cmgp_usi0_pclk           0        0        0   399750000
>        gout_gpio_cmgp_pclk           0        0        0   399750000
>        dout_cmgp_adc                 0        0        0    28553572
>        mout_cmgp_usi1                0        0        0   399750000
>           dout_cmgp_usi1             0        0        0   199875000
>              gout_cmgp_usi1_ipclk    0        0        0   199875000
>        mout_cmgp_usi0                0        0        0   399750000
>           dout_cmgp_usi0             0        0        0   199875000
>              gout_cmgp_usi0_ipclk    0        0        0   199875000
> <<<<<<<<<<<<<<<<<<<<<<<<<<<< cut here >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
>
> [1] https://lkml.org/lkml/2021/10/22/979
>
> Sam Protsenko (2):
>   dt-bindings: clock: samsung: Document Exynos850 CMU_CMGP
>   clk: samsung: exynos850: Implement CMU_CMGP domain
>
>  .../clock/samsung,exynos850-clock.yaml        |  19 ++++
>  drivers/clk/samsung/clk-exynos850.c           | 100 ++++++++++++++++++
>  include/dt-bindings/clock/exynos850.h         |  17 +++
>  3 files changed, 136 insertions(+)
>
> --

Hi Sylwester,

Can you please review my patches I've submitted recently? Those are:

  - [PATCH 1/2] dt-bindings: clock: samsung: Document Exynos850 CMU_APM
  - [PATCH 2/2] clk: samsung: exynos850: Implement CMU_APM domain
  - [PATCH 1/1] clk: samsung: exynos850: Register clocks early
  - [PATCH 0/2] clk: samsung: exynos850: Implement CMU_CMGP
  - [PATCH 1/2] dt-bindings: clock: samsung: Document Exynos850 CMU_CMGP
  - [PATCH 2/2] clk: samsung: exynos850: Implement CMU_CMGP domain

My further series (like device tree patches for new dev board support)
depend on the status of above patches. So it'd great if those can be
reviewed and applied if it's feasible.

Thanks!

> 2.30.2
>