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Message-ID: <1b9cdfba-6436-f2bd-d67b-7528758a6c35@kernel.org>
Date: Mon, 22 Nov 2021 17:25:03 +0200
From: Georgi Djakov <djakov@...nel.org>
To: Bjorn Andersson <bjorn.andersson@...aro.org>,
Odelu Kukatla <okukatla@...eaurora.org>,
georgi.djakov@...aro.org
Cc: evgreen@...gle.com, Andy Gross <agross@...nel.org>,
linux-arm-msm@...r.kernel.org, linux-pm@...r.kernel.org,
linux-kernel@...r.kernel.org, sboyd@...nel.org,
mdtipton@...eaurora.org, sibis@...eaurora.org,
saravanak@...gle.com, seansw@....qualcomm.com, elder@...aro.org,
linux-arm-msm-owner@...r.kernel.org
Subject: Re: [v8 2/3] interconnect: qcom: Add EPSS L3 support on SC7280
On 18.11.21 22:53, Bjorn Andersson wrote:
> On Thu 21 Oct 05:40 CDT 2021, Odelu Kukatla wrote:
>
>> Add Epoch Subsystem (EPSS) L3 interconnect provider support on
>> SC7280 SoCs.
>>
>
> Reviewed-by: Bjorn Andersson <bjorn.andersson@...aro.org>
Thanks!
> @Georgi, do you intend to apply the two interconnect patches in this
> series?
Yes, applied!
BR,
Georgi
>
> Regards,
> Bjorn
>
>> Signed-off-by: Odelu Kukatla <okukatla@...eaurora.org>
>> ---
>> drivers/interconnect/qcom/osm-l3.c | 20 +++++++++++++++++++-
>> drivers/interconnect/qcom/sc7280.h | 2 ++
>> 2 files changed, 21 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c
>> index c7af143..eec1309 100644
>> --- a/drivers/interconnect/qcom/osm-l3.c
>> +++ b/drivers/interconnect/qcom/osm-l3.c
>> @@ -1,6 +1,6 @@
>> // SPDX-License-Identifier: GPL-2.0
>> /*
>> - * Copyright (c) 2020, The Linux Foundation. All rights reserved.
>> + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
>> */
>>
>> #include <linux/bitfield.h>
>> @@ -15,6 +15,7 @@
>> #include <dt-bindings/interconnect/qcom,osm-l3.h>
>>
>> #include "sc7180.h"
>> +#include "sc7280.h"
>> #include "sc8180x.h"
>> #include "sdm845.h"
>> #include "sm8150.h"
>> @@ -114,6 +115,22 @@ static const struct qcom_osm_l3_desc sc7180_icc_osm_l3 = {
>> .reg_perf_state = OSM_REG_PERF_STATE,
>> };
>>
>> +DEFINE_QNODE(sc7280_epss_apps_l3, SC7280_MASTER_EPSS_L3_APPS, 32, SC7280_SLAVE_EPSS_L3);
>> +DEFINE_QNODE(sc7280_epss_l3, SC7280_SLAVE_EPSS_L3, 32);
>> +
>> +static const struct qcom_osm_l3_node *sc7280_epss_l3_nodes[] = {
>> + [MASTER_EPSS_L3_APPS] = &sc7280_epss_apps_l3,
>> + [SLAVE_EPSS_L3_SHARED] = &sc7280_epss_l3,
>> +};
>> +
>> +static const struct qcom_osm_l3_desc sc7280_icc_epss_l3 = {
>> + .nodes = sc7280_epss_l3_nodes,
>> + .num_nodes = ARRAY_SIZE(sc7280_epss_l3_nodes),
>> + .lut_row_size = EPSS_LUT_ROW_SIZE,
>> + .reg_freq_lut = EPSS_REG_FREQ_LUT,
>> + .reg_perf_state = EPSS_REG_PERF_STATE,
>> +};
>> +
>> DEFINE_QNODE(sc8180x_osm_apps_l3, SC8180X_MASTER_OSM_L3_APPS, 32, SC8180X_SLAVE_OSM_L3);
>> DEFINE_QNODE(sc8180x_osm_l3, SC8180X_SLAVE_OSM_L3, 32);
>>
>> @@ -326,6 +343,7 @@ static int qcom_osm_l3_probe(struct platform_device *pdev)
>>
>> static const struct of_device_id osm_l3_of_match[] = {
>> { .compatible = "qcom,sc7180-osm-l3", .data = &sc7180_icc_osm_l3 },
>> + { .compatible = "qcom,sc7280-epss-l3", .data = &sc7280_icc_epss_l3 },
>> { .compatible = "qcom,sdm845-osm-l3", .data = &sdm845_icc_osm_l3 },
>> { .compatible = "qcom,sm8150-osm-l3", .data = &sm8150_icc_osm_l3 },
>> { .compatible = "qcom,sc8180x-osm-l3", .data = &sc8180x_icc_osm_l3 },
>> diff --git a/drivers/interconnect/qcom/sc7280.h b/drivers/interconnect/qcom/sc7280.h
>> index 175e400..1fb9839 100644
>> --- a/drivers/interconnect/qcom/sc7280.h
>> +++ b/drivers/interconnect/qcom/sc7280.h
>> @@ -150,5 +150,7 @@
>> #define SC7280_SLAVE_PCIE_1 139
>> #define SC7280_SLAVE_QDSS_STM 140
>> #define SC7280_SLAVE_TCU 141
>> +#define SC7280_MASTER_EPSS_L3_APPS 142
>> +#define SC7280_SLAVE_EPSS_L3 143
>>
>> #endif
>> --
>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
>> a Linux Foundation Collaborative Project
>>
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