Message-ID: <9930802.MB9u6SvQ6m@diego>
Date:   Mon, 29 Nov 2021 13:06:23 +0100
From:   Heiko Stübner <heiko@...ech.de>
To:     wefu@...hat.com, linux-riscv@...ts.infradead.org
Cc:     linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
        taiten.peng@...onical.com, aniket.ponkshe@...onical.com,
        gordan.markus@...onical.com, guoren@...ux.alibaba.com,
        arnd@...db.de, wens@...e.org, maxime@...no.tech,
        dlustig@...dia.com, gfavor@...tanamicro.com,
        andrea.mondelli@...wei.com, behrensj@....edu, xinhaoqu@...wei.com,
        huffman@...ence.com, mick@....forth.gr,
        allen.baum@...erantotech.com, jscheid@...tanamicro.com,
        rtrauben@...il.com, Anup Patel <anup@...infault.org>,
        Rob Herring <robh+dt@...nel.org>, anup.patel@....com,
        atishp04@...il.com, palmer@...belt.com, guoren@...nel.org,
        christoph.muellner@...ll.eu, philipp.tomsich@...ll.eu, hch@....de,
        liush@...winnertech.com, lazyparser@...il.com,
        drew@...gleboard.org,
        Heinrich Schuchardt <heinrich.schuchardt@...onical.com>
Subject: Re: [PATCH V4 1/2] dt-bindings: riscv: add MMU Standard Extensions support for Svpbmt

Am Montag, 29. November 2021, 09:54:39 CET schrieb Heinrich Schuchardt:
> On 11/29/21 02:40, wefu@...hat.com wrote:
> > From: Wei Fu <wefu@...hat.com>
> > 
> > Previous patch has added svpbmt in arch/riscv and add "riscv,svpmbt"
> > in the DT mmu node. Update dt-bindings related property here.
> > 
> > Signed-off-by: Wei Fu <wefu@...hat.com>
> > Co-developed-by: Guo Ren <guoren@...nel.org>
> > Signed-off-by: Guo Ren <guoren@...nel.org>
> > Cc: Anup Patel <anup@...infault.org>
> > Cc: Palmer Dabbelt <palmer@...belt.com>
> > Cc: Rob Herring <robh+dt@...nel.org>
> > ---
> >   Documentation/devicetree/bindings/riscv/cpus.yaml | 10 ++++++++++
> >   1 file changed, 10 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > index aa5fb64d57eb..9ff9cbdd8a85 100644
> > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > @@ -63,6 +63,16 @@ properties:
> >         - riscv,sv48
> >         - riscv,none
> >   
> > +  mmu:
> 
> Shouldn't we keep the items be in alphabetic order, i.e. mmu before 
> mmu-type?
> 
> > +    description:
> > +      Describes the CPU's MMU Standard Extensions support.
> > +      These values originate from the RISC-V Privileged
> > +      Specification document, available from
> > +      https://riscv.org/specifications/
> > +    $ref: '/schemas/types.yaml#/definitions/string'
> > +    enum:
> > +      - riscv,svpmbt
> 
> The privileged specification has multiple MMU related extensions: 
> Svnapot, Svpbmt, Svinval. Shall they all be modeled in this enum?

I remember in some earlier version some way back there was the
suggestion of using a sub-node instead and then adding boolean
properties for the supported extensions.

Aka something like
	mmu {
		riscv,svpbmt;	
	};

Which I guess would be a lot nicer. Also right now there is string-
comparison done on the code side, which would look way easier
when just looking for booleans in the dt instead.

Also isn't an enum a "one-of" selection, so wouldn't work directly
for multiple extensions?


Heiko


> 
> Best regards
> 
> Heinrich
> 
> > +
> >     riscv,isa:
> >       description:
> >         Identifies the specific RISC-V instruction set architecture
> > 
> 
> 
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