linux-kernel - Re: [PATCH v2 2/5] MIPS: ralink: implement 'pcibios_root_bridge

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Message-ID: <d243a90d-25b2-a65f-b69d-af7497db8742@roeck-us.net>
Date:   Wed, 1 Dec 2021 14:17:07 -0800
From:   Guenter Roeck <linux@...ck-us.net>
To:     Sergio Paracuellos <sergio.paracuellos@...il.com>,
        linux-pci@...r.kernel.org
Cc:     linux-mips@...r.kernel.org, tsbogend@...ha.franken.de,
        lorenzo.pieralisi@....com, bhelgaas@...gle.com, arnd@...db.de,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 2/5] MIPS: ralink: implement
 'pcibios_root_bridge_prepare()'

On 12/1/21 1:51 PM, Sergio Paracuellos wrote:
> PCI core code call 'pcibios_root_bridge_prepare()' function inside function
> 'pci_register_host_bridge()'. This point is very good way to properly enter
> into this MIPS ralink specific code to properly setup I/O coherency units
> with PCI memory addresses.
> 
> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@...il.com>
> ---
>   arch/mips/ralink/mt7621.c | 30 ++++++++++++++++++++++++++++++
>   1 file changed, 30 insertions(+)
> 
> diff --git a/arch/mips/ralink/mt7621.c b/arch/mips/ralink/mt7621.c
> index bd71f5b14238..7649416c1cd7 100644
> --- a/arch/mips/ralink/mt7621.c
> +++ b/arch/mips/ralink/mt7621.c
> @@ -10,6 +10,7 @@
>   #include <linux/slab.h>
>   #include <linux/sys_soc.h>
>   #include <linux/memblock.h>
> +#include <linux/pci.h>
>   
>   #include <asm/bootinfo.h>
>   #include <asm/mipsregs.h>
> @@ -22,6 +23,35 @@
>   
>   static void *detect_magic __initdata = detect_memory_region;
>   
> +int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
> +{
> +	struct resource_entry *entry;
> +	resource_size_t mask;
> +
> +	entry = resource_list_first_type(&bridge->windows, IORESOURCE_MEM);
> +	if (!entry) {
> +		pr_err("Cannot get memory resource\n");
> +		return -EINVAL;
> +	}
> +
> +	if (mips_cps_numiocu(0)) {
> +		/*
> +		 * FIXME: hardware doesn't accept mask values with 1s after
> +		 * 0s (e.g. 0xffef), so it would be great to warn if that's
> +		 * about to happen
> +		 */ > +		mask = ~(entry->res->end - entry->res->start);
> +

Try something like this:
		WARN_ON((mask != ~0UL && BIT(ffz(mask)) - 1 != mask);

> +		write_gcr_reg1_base(entry->res->start);
> +		write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
> +		pr_info("PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n",
> +			(unsigned long long)read_gcr_reg1_base(),
> +			(unsigned long long)read_gcr_reg1_mask());
> +	}
> +
> +	return 0;
> +}
> +
>   phys_addr_t mips_cpc_default_phys_base(void)
>   {
>   	panic("Cannot detect cpc address");
>