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Message-ID: <758d3f36-b6ad-d849-191e-4180e7e80c18@linaro.org>
Date: Wed, 1 Dec 2021 15:09:35 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Vinod Koul <vkoul@...nel.org>, Stephen Boyd <sboyd@...nel.org>,
Rob Herring <robh+dt@...nel.org>
Cc: linux-arm-msm@...r.kernel.org,
Bjorn Andersson <bjorn.andersson@...aro.org>,
Andy Gross <agross@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Vamsi Krishna Lanka <quic_vamslank@...cinc.com>,
linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH 3/4] clk: qcom: Add clock driver for SM8450
On 01/12/2021 10:23, Vinod Koul wrote:
> This adds Global Clock controller (GCC) driver for SM8450 SoC including
> the gcc resets and gdsc.
>
> This patch is based on initial code downstream by Vivek Aknurwar
> <viveka@...eaurora.org>
>
> Signed-off-by: Vinod Koul <vkoul@...nel.org>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
> ---
> drivers/clk/qcom/Kconfig | 8 +
> drivers/clk/qcom/Makefile | 1 +
> drivers/clk/qcom/gcc-sm8450.c | 3314 +++++++++++++++++++++++++++++++++
> 3 files changed, 3323 insertions(+)
> create mode 100644 drivers/clk/qcom/gcc-sm8450.c
>
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 74efc82127e1..3a568e7ad886 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -618,6 +618,14 @@ config SM_GCC_8350
> Say Y if you want to use peripheral devices such as UART,
> SPI, I2C, USB, SD/UFS, PCIe etc.
>
> +config SM_GCC_8450
> + tristate "SM8450 Global Clock Controller"
> + select QCOM_GDSC
> + help
> + Support for the global clock controller on SM8450 devices.
> + Say Y if you want to use peripheral devices such as UART,
> + SPI, I2C, USB, SD/UFS, PCIe etc.
> +
> config SM_GPUCC_8150
> tristate "SM8150 Graphics Clock Controller"
> select SM_GCC_8150
> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> index 1718c34d3551..efb0837ea199 100644
> --- a/drivers/clk/qcom/Makefile
> +++ b/drivers/clk/qcom/Makefile
> @@ -90,6 +90,7 @@ obj-$(CONFIG_SM_GCC_6350) += gcc-sm6350.o
> obj-$(CONFIG_SM_GCC_8150) += gcc-sm8150.o
> obj-$(CONFIG_SM_GCC_8250) += gcc-sm8250.o
> obj-$(CONFIG_SM_GCC_8350) += gcc-sm8350.o
> +obj-$(CONFIG_SM_GCC_8450) += gcc-sm8450.o
> obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o
> obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o
> obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o
> diff --git a/drivers/clk/qcom/gcc-sm8450.c b/drivers/clk/qcom/gcc-sm8450.c
> new file mode 100644
> index 000000000000..175c18a1cdbe
> --- /dev/null
> +++ b/drivers/clk/qcom/gcc-sm8450.c
> @@ -0,0 +1,3314 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2021, Linaro Limited
> + */
> +
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/regmap.h>
> +
> +#include <dt-bindings/clock/qcom,gcc-sm8450.h>
> +
> +#include "clk-alpha-pll.h"
> +#include "clk-branch.h"
> +#include "clk-rcg.h"
> +#include "clk-regmap.h"
> +#include "clk-regmap-divider.h"
> +#include "clk-regmap-mux.h"
> +#include "gdsc.h"
> +#include "reset.h"
> +
> +enum {
> + P_BI_TCXO,
> + P_GCC_GPLL0_OUT_EVEN,
> + P_GCC_GPLL0_OUT_MAIN,
> + P_GCC_GPLL4_OUT_MAIN,
> + P_GCC_GPLL9_OUT_MAIN,
> + P_PCIE_0_PIPE_CLK,
> + P_PCIE_1_PHY_AUX_CLK,
> + P_PCIE_1_PIPE_CLK,
> + P_SLEEP_CLK,
> + P_UFS_PHY_RX_SYMBOL_0_CLK,
> + P_UFS_PHY_RX_SYMBOL_1_CLK,
> + P_UFS_PHY_TX_SYMBOL_0_CLK,
> + P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
> +};
> +
> +static struct clk_alpha_pll gcc_gpll0 = {
> + .offset = 0x0,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
> + .clkr = {
> + .enable_reg = 0x62018,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_gpll0",
> + .parent_data = &(const struct clk_parent_data){
> + .fw_name = "bi_tcxo",
> + .name = "bi_tcxo",
> + },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_fixed_lucid_evo_ops,
> + },
> + },
> +};
> +
> +static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
> + { 0x1, 2 },
> + { }
> +};
> +
> +static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
> + .offset = 0x0,
> + .post_div_shift = 10,
> + .post_div_table = post_div_table_gcc_gpll0_out_even,
> + .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
> + .width = 4,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "gcc_gpll0_out_even",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_gpll0.clkr.hw,
> + },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
> + },
> +};
> +
> +static struct clk_alpha_pll gcc_gpll4 = {
> + .offset = 0x4000,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
> + .clkr = {
> + .enable_reg = 0x62018,
> + .enable_mask = BIT(4),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_gpll4",
> + .parent_data = &(const struct clk_parent_data){
> + .fw_name = "bi_tcxo",
> + .name = "bi_tcxo",
> + },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_fixed_lucid_evo_ops,
> + },
> + },
> +};
> +
> +static struct clk_alpha_pll gcc_gpll9 = {
> + .offset = 0x9000,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
> + .clkr = {
> + .enable_reg = 0x62018,
> + .enable_mask = BIT(9),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_gpll9",
> + .parent_data = &(const struct clk_parent_data){
> + .fw_name = "bi_tcxo",
> + .name = "bi_tcxo",
> + },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_fixed_lucid_evo_ops,
> + },
> + },
> +};
> +
> +static const struct parent_map gcc_parent_map_0[] = {
> + { P_BI_TCXO, 0 },
> + { P_GCC_GPLL0_OUT_MAIN, 1 },
> + { P_GCC_GPLL0_OUT_EVEN, 6 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_0[] = {
> + { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
> + { .hw = &gcc_gpll0.clkr.hw },
> + { .hw = &gcc_gpll0_out_even.clkr.hw },
> +};
> +
> +static const struct parent_map gcc_parent_map_1[] = {
> + { P_BI_TCXO, 0 },
> + { P_GCC_GPLL0_OUT_MAIN, 1 },
> + { P_SLEEP_CLK, 5 },
> + { P_GCC_GPLL0_OUT_EVEN, 6 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_1[] = {
> + { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
> + { .hw = &gcc_gpll0.clkr.hw },
> + { .fw_name = "sleep_clk", .name = "sleep_clk" },
> + { .hw = &gcc_gpll0_out_even.clkr.hw },
> +};
> +
> +static const struct parent_map gcc_parent_map_2[] = {
> + { P_BI_TCXO, 0 },
> + { P_SLEEP_CLK, 5 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_2[] = {
> + { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
> + { .fw_name = "sleep_clk", .name = "sleep_clk" },
> +};
> +
> +static const struct parent_map gcc_parent_map_3[] = {
> + { P_BI_TCXO, 0 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_3[] = {
> + { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
> +};
> +
> +static const struct parent_map gcc_parent_map_4[] = {
> + { P_PCIE_0_PIPE_CLK, 0 },
> + { P_BI_TCXO, 2 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_4[] = {
> + { .fw_name = "pcie_0_pipe_clk", },
> + { .fw_name = "bi_tcxo", },
> +};
> +
> +static const struct parent_map gcc_parent_map_5[] = {
> + { P_PCIE_1_PHY_AUX_CLK, 0 },
> + { P_BI_TCXO, 2 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_5[] = {
> + { .fw_name = "pcie_1_phy_aux_clk", .name = "pcie_1_phy_aux_clk" },
> + { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
> +};
> +
> +static const struct parent_map gcc_parent_map_6[] = {
> + { P_PCIE_1_PIPE_CLK, 0 },
> + { P_BI_TCXO, 2 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_6[] = {
> + { .fw_name = "pcie_1_pipe_clk", .name = "pcie_1_pipe_clk" },
> + { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
> +};
> +
> +static const struct parent_map gcc_parent_map_7[] = {
> + { P_BI_TCXO, 0 },
> + { P_GCC_GPLL0_OUT_MAIN, 1 },
> + { P_GCC_GPLL9_OUT_MAIN, 2 },
> + { P_GCC_GPLL4_OUT_MAIN, 5 },
> + { P_GCC_GPLL0_OUT_EVEN, 6 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_7[] = {
> + { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
> + { .hw = &gcc_gpll0.clkr.hw },
> + { .hw = &gcc_gpll9.clkr.hw },
> + { .hw = &gcc_gpll4.clkr.hw },
> + { .hw = &gcc_gpll0_out_even.clkr.hw },
> +};
> +
> +static const struct parent_map gcc_parent_map_8[] = {
> + { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
> + { P_BI_TCXO, 2 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_8[] = {
> + { .fw_name = "ufs_phy_rx_symbol_0_clk", .name = "ufs_phy_rx_symbol_0_clk" },
> + { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
> +};
> +
> +static const struct parent_map gcc_parent_map_9[] = {
> + { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
> + { P_BI_TCXO, 2 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_9[] = {
> + { .fw_name = "ufs_phy_rx_symbol_1_clk", .name = "ufs_phy_rx_symbol_1_clk" },
> + { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
> +};
> +
> +static const struct parent_map gcc_parent_map_10[] = {
> + { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
> + { P_BI_TCXO, 2 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_10[] = {
> + { .fw_name = "ufs_phy_tx_symbol_0_clk", .name = "ufs_phy_tx_symbol_0_clk" },
> + { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
> +};
> +
> +static const struct parent_map gcc_parent_map_11[] = {
> + { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
> + { P_BI_TCXO, 2 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_11[] = {
> + { .fw_name = "usb3_phy_wrapper_gcc_usb30_pipe_clk", .name =
> + "usb3_phy_wrapper_gcc_usb30_pipe_clk" },
> + { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
> +};
> +
> +static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = {
> + .reg = 0x7b060,
> + .shift = 0,
> + .width = 2,
> + .parent_map = gcc_parent_map_4,
> + .clkr = {
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_pcie_0_pipe_clk_src",
> + .parent_data = gcc_parent_data_4,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_4),
> + .ops = &clk_regmap_mux_closest_ops,
> + },
> + },
> +};
> +
> +static struct clk_regmap_mux gcc_pcie_1_phy_aux_clk_src = {
> + .reg = 0x9d080,
> + .shift = 0,
> + .width = 2,
> + .parent_map = gcc_parent_map_5,
> + .clkr = {
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_pcie_1_phy_aux_clk_src",
> + .parent_data = gcc_parent_data_5,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_5),
> + .ops = &clk_regmap_mux_closest_ops,
> + },
> + },
> +};
> +
> +static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = {
> + .reg = 0x9d064,
> + .shift = 0,
> + .width = 2,
> + .parent_map = gcc_parent_map_6,
> + .clkr = {
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_pcie_1_pipe_clk_src",
> + .parent_data = gcc_parent_data_6,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_6),
> + .ops = &clk_regmap_mux_closest_ops,
> + },
> + },
> +};
> +
> +static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = {
> + .reg = 0x87060,
> + .shift = 0,
> + .width = 2,
> + .parent_map = gcc_parent_map_8,
> + .clkr = {
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_ufs_phy_rx_symbol_0_clk_src",
> + .parent_data = gcc_parent_data_8,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_8),
> + .ops = &clk_regmap_mux_closest_ops,
> + },
> + },
> +};
> +
> +static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = {
> + .reg = 0x870d0,
> + .shift = 0,
> + .width = 2,
> + .parent_map = gcc_parent_map_9,
> + .clkr = {
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_ufs_phy_rx_symbol_1_clk_src",
> + .parent_data = gcc_parent_data_9,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_9),
> + .ops = &clk_regmap_mux_closest_ops,
> + },
> + },
> +};
> +
> +static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = {
> + .reg = 0x87050,
> + .shift = 0,
> + .width = 2,
> + .parent_map = gcc_parent_map_10,
> + .clkr = {
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_ufs_phy_tx_symbol_0_clk_src",
> + .parent_data = gcc_parent_data_10,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_10),
> + .ops = &clk_regmap_mux_closest_ops,
> + },
> + },
> +};
> +
> +static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
> + .reg = 0x49068,
> + .shift = 0,
> + .width = 2,
> + .parent_map = gcc_parent_map_11,
> + .clkr = {
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_usb3_prim_phy_pipe_clk_src",
> + .parent_data = gcc_parent_data_11,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_11),
> + .ops = &clk_regmap_mux_closest_ops,
> + },
> + },
> +};
> +
> +static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
> + F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
> + F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
> + F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gcc_gp1_clk_src = {
> + .cmd_rcgr = 0x74004,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_1,
> + .freq_tbl = ftbl_gcc_gp1_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "gcc_gp1_clk_src",
> + .parent_data = gcc_parent_data_1,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_1),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 gcc_gp2_clk_src = {
> + .cmd_rcgr = 0x75004,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_1,
> + .freq_tbl = ftbl_gcc_gp1_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "gcc_gp2_clk_src",
> + .parent_data = gcc_parent_data_1,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_1),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 gcc_gp3_clk_src = {
> + .cmd_rcgr = 0x76004,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_1,
> + .freq_tbl = ftbl_gcc_gp1_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "gcc_gp3_clk_src",
> + .parent_data = gcc_parent_data_1,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_1),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
> + F(19200000, P_BI_TCXO, 1, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
> + .cmd_rcgr = 0x7b064,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_2,
> + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "gcc_pcie_0_aux_clk_src",
> + .parent_data = gcc_parent_data_2,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_2),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
> + F(19200000, P_BI_TCXO, 1, 0, 0),
> + F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
> + .cmd_rcgr = 0x7b048,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_0,
> + .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "gcc_pcie_0_phy_rchng_clk_src",
> + .parent_data = gcc_parent_data_0,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
> + .cmd_rcgr = 0x9d068,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_2,
> + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "gcc_pcie_1_aux_clk_src",
> + .parent_data = gcc_parent_data_2,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_2),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {
> + .cmd_rcgr = 0x9d04c,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_0,
> + .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "gcc_pcie_1_phy_rchng_clk_src",
> + .parent_data = gcc_parent_data_0,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
> + F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gcc_pdm2_clk_src = {
> + .cmd_rcgr = 0x43010,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_0,
> + .freq_tbl = ftbl_gcc_pdm2_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "gcc_pdm2_clk_src",
> + .parent_data = gcc_parent_data_0,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
> + F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
> + F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
> + F(19200000, P_BI_TCXO, 1, 0, 0),
> + F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
> + F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
> + F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
> + F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
> + F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
> + F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
> + F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
> + F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
> + { }
> +};
> +
> +static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
> + .name = "gcc_qupv3_wrap0_s0_clk_src",
> + .parent_data = gcc_parent_data_0,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
> +};
> +
> +static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
> + .cmd_rcgr = 0x27014,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_0,
> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
> + .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
> +};
> +
> +static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
> + .name = "gcc_qupv3_wrap0_s1_clk_src",
> + .parent_data = gcc_parent_data_0,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
> +};
> +
> +static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
> + .cmd_rcgr = 0x27148,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_0,
> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
> + .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
> +};
> +
> +static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
> + .name = "gcc_qupv3_wrap0_s2_clk_src",
> + .parent_data = gcc_parent_data_0,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
> +};
> +
> +static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
> + .cmd_rcgr = 0x2727c,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_0,
> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
> + .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
> +};
> +
> +static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
> + .name = "gcc_qupv3_wrap0_s3_clk_src",
> + .parent_data = gcc_parent_data_0,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
> +};
> +
> +static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
> + .cmd_rcgr = 0x273b0,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_0,
> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
> + .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
> +};
> +
> +static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
> + .name = "gcc_qupv3_wrap0_s4_clk_src",
> + .parent_data = gcc_parent_data_0,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
> +};
> +
> +static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
> + .cmd_rcgr = 0x274e4,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_0,
> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
> + .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
> +};
> +
> +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s5_clk_src[] = {
> + F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
> + F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
> + F(19200000, P_BI_TCXO, 1, 0, 0),
> + F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
> + F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
> + F(37500000, P_GCC_GPLL0_OUT_EVEN, 8, 0, 0),
> + F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
> + F(50000000, P_GCC_GPLL0_OUT_MAIN, 12, 0, 0),
> + { }
> +};
> +
> +static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
> + .name = "gcc_qupv3_wrap0_s5_clk_src",
> + .parent_data = gcc_parent_data_0,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
> +};
> +
> +static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
> + .cmd_rcgr = 0x27618,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_0,
> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s5_clk_src,
> + .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
> +};
> +
> +static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
> + .name = "gcc_qupv3_wrap0_s6_clk_src",
> + .parent_data = gcc_parent_data_0,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
> +};
> +
> +static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
> + .cmd_rcgr = 0x2774c,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_0,
> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
> + .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
> +};
> +
> +static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
> + .name = "gcc_qupv3_wrap0_s7_clk_src",
> + .parent_data = gcc_parent_data_0,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
> +};
> +
> +static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
> + .cmd_rcgr = 0x27880,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_0,
> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
> + .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
> +};
> +
> +static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s0_clk_src[] = {
> + F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
> + F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
> + F(19200000, P_BI_TCXO, 1, 0, 0),
> + F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
> + F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
> + F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
> + F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
> + F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
> + F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
> + F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
> + F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
> + F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375),
> + F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75),
> + F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625),
> + F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
> + { }
> +};
> +
> +static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
> + .name = "gcc_qupv3_wrap1_s0_clk_src",
> + .parent_data = gcc_parent_data_0,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
> +};
> +
> +static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
> + .cmd_rcgr = 0x28014,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_0,
> + .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
> + .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
> +};
> +
> +static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
> + .name = "gcc_qupv3_wrap1_s1_clk_src",
> + .parent_data = gcc_parent_data_0,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
> +};
> +
> +static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
> + .cmd_rcgr = 0x28148,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_0,
> + .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
> + .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
> +};
> +
> +static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
> + .name = "gcc_qupv3_wrap1_s2_clk_src",
> + .parent_data = gcc_parent_data_0,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
> +};
> +
> +static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
> + .cmd_rcgr = 0x2827c,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_0,
> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
> + .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
> +};
> +
> +static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
> + .name = "gcc_qupv3_wrap1_s3_clk_src",
> + .parent_data = gcc_parent_data_0,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
> +};
> +
> +static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
> + .cmd_rcgr = 0x283b0,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_0,
> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
> + .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
> +};
> +
> +static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
> + .name = "gcc_qupv3_wrap1_s4_clk_src",
> + .parent_data = gcc_parent_data_0,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
> +};
> +
> +static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
> + .cmd_rcgr = 0x284e4,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_0,
> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
> + .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
> +};
> +
> +static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
> + .name = "gcc_qupv3_wrap1_s5_clk_src",
> + .parent_data = gcc_parent_data_0,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
> +};
> +
> +static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
> + .cmd_rcgr = 0x28618,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_0,
> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
> + .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
> +};
> +
> +static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
> + .name = "gcc_qupv3_wrap1_s6_clk_src",
> + .parent_data = gcc_parent_data_0,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
> +};
> +
> +static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
> + .cmd_rcgr = 0x2874c,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_0,
> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
> + .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,
> +};
> +
> +static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
> + .name = "gcc_qupv3_wrap2_s0_clk_src",
> + .parent_data = gcc_parent_data_0,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
> +};
> +
> +static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
> + .cmd_rcgr = 0x2e014,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_0,
> + .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
> + .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,
> +};
> +
> +static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
> + .name = "gcc_qupv3_wrap2_s1_clk_src",
> + .parent_data = gcc_parent_data_0,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
> +};
> +
> +static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
> + .cmd_rcgr = 0x2e148,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_0,
> + .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
> + .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,
> +};
> +
> +static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
> + .name = "gcc_qupv3_wrap2_s2_clk_src",
> + .parent_data = gcc_parent_data_0,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
> +};
> +
> +static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
> + .cmd_rcgr = 0x2e27c,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_0,
> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
> + .clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init,
> +};
> +
> +static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
> + .name = "gcc_qupv3_wrap2_s3_clk_src",
> + .parent_data = gcc_parent_data_0,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
> +};
> +
> +static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
> + .cmd_rcgr = 0x2e3b0,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_0,
> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
> + .clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init,
> +};
> +
> +static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
> + .name = "gcc_qupv3_wrap2_s4_clk_src",
> + .parent_data = gcc_parent_data_0,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
> +};
> +
> +static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
> + .cmd_rcgr = 0x2e4e4,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_0,
> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
> + .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,
> +};
> +
> +static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
> + .name = "gcc_qupv3_wrap2_s5_clk_src",
> + .parent_data = gcc_parent_data_0,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
> +};
> +
> +static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
> + .cmd_rcgr = 0x2e618,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_0,
> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
> + .clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,
> +};
> +
> +static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = {
> + .name = "gcc_qupv3_wrap2_s6_clk_src",
> + .parent_data = gcc_parent_data_0,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
> +};
> +
> +static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {
> + .cmd_rcgr = 0x2e74c,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_0,
> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
> + .clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init,
> +};
> +
> +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
> + F(400000, P_BI_TCXO, 12, 1, 4),
> + F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
> + F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
> + F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
> + F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
> + .cmd_rcgr = 0x24014,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_7,
> + .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "gcc_sdcc2_apps_clk_src",
> + .parent_data = gcc_parent_data_7,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_7),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
> + F(400000, P_BI_TCXO, 12, 1, 4),
> + F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
> + F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
> + .cmd_rcgr = 0x26014,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_0,
> + .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "gcc_sdcc4_apps_clk_src",
> + .parent_data = gcc_parent_data_0,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
> + F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
> + F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
> + F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
> + F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
> + .cmd_rcgr = 0x8702c,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_0,
> + .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "gcc_ufs_phy_axi_clk_src",
> + .parent_data = gcc_parent_data_0,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
> + F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
> + F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
> + F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
> + .cmd_rcgr = 0x87074,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_0,
> + .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "gcc_ufs_phy_ice_core_clk_src",
> + .parent_data = gcc_parent_data_0,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = {
> + F(9600000, P_BI_TCXO, 2, 0, 0),
> + F(19200000, P_BI_TCXO, 1, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
> + .cmd_rcgr = 0x870a8,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_3,
> + .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "gcc_ufs_phy_phy_aux_clk_src",
> + .parent_data = gcc_parent_data_3,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_3),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
> + .cmd_rcgr = 0x8708c,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_0,
> + .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "gcc_ufs_phy_unipro_core_clk_src",
> + .parent_data = gcc_parent_data_0,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
> + F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
> + F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
> + F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
> + F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
> + .cmd_rcgr = 0x49028,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_0,
> + .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "gcc_usb30_prim_master_clk_src",
> + .parent_data = gcc_parent_data_0,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
> + .cmd_rcgr = 0x49040,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_0,
> + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "gcc_usb30_prim_mock_utmi_clk_src",
> + .parent_data = gcc_parent_data_0,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
> + .cmd_rcgr = 0x4906c,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_2,
> + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "gcc_usb3_prim_phy_aux_clk_src",
> + .parent_data = gcc_parent_data_2,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_2),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
> + .reg = 0x49058,
> + .shift = 0,
> + .width = 4,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_regmap_div_ro_ops,
> + },
> +};
> +
> +static struct clk_branch gcc_aggre_noc_pcie_0_axi_clk = {
> + .halt_reg = 0x7b08c,
> + .halt_check = BRANCH_HALT_SKIP,
> + .hwcg_reg = 0x7b08c,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x62000,
> + .enable_mask = BIT(12),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_aggre_noc_pcie_0_axi_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_aggre_noc_pcie_1_axi_clk = {
> + .halt_reg = 0x9d098,
> + .halt_check = BRANCH_HALT_SKIP,
> + .hwcg_reg = 0x9d098,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x62000,
> + .enable_mask = BIT(11),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_aggre_noc_pcie_1_axi_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
> + .halt_reg = 0x870d4,
> + .halt_check = BRANCH_HALT_VOTED,
> + .hwcg_reg = 0x870d4,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x870d4,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_aggre_ufs_phy_axi_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
> + .halt_reg = 0x870d4,
> + .halt_check = BRANCH_HALT_VOTED,
> + .hwcg_reg = 0x870d4,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x870d4,
> + .enable_mask = BIT(1),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
> + .halt_reg = 0x49088,
> + .halt_check = BRANCH_HALT_VOTED,
> + .hwcg_reg = 0x49088,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x49088,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_aggre_usb3_prim_axi_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_boot_rom_ahb_clk = {
> + .halt_reg = 0x48004,
> + .halt_check = BRANCH_HALT_VOTED,
> + .hwcg_reg = 0x48004,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x62000,
> + .enable_mask = BIT(10),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_boot_rom_ahb_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_camera_hf_axi_clk = {
> + .halt_reg = 0x36010,
> + .halt_check = BRANCH_HALT_SKIP,
> + .hwcg_reg = 0x36010,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x36010,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_camera_hf_axi_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_camera_sf_axi_clk = {
> + .halt_reg = 0x36018,
> + .halt_check = BRANCH_HALT_SKIP,
> + .hwcg_reg = 0x36018,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x36018,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_camera_sf_axi_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_cfg_noc_pcie_anoc_ahb_clk = {
> + .halt_reg = 0x20030,
> + .halt_check = BRANCH_HALT_VOTED,
> + .hwcg_reg = 0x20030,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x62000,
> + .enable_mask = BIT(20),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_cfg_noc_pcie_anoc_ahb_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
> + .halt_reg = 0x49084,
> + .halt_check = BRANCH_HALT_VOTED,
> + .hwcg_reg = 0x49084,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x49084,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_cfg_noc_usb3_prim_axi_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_ddrss_gpu_axi_clk = {
> + .halt_reg = 0x81154,
> + .halt_check = BRANCH_HALT_SKIP,
> + .hwcg_reg = 0x81154,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x81154,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_ddrss_gpu_axi_clk",
> + .ops = &clk_branch2_aon_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_ddrss_pcie_sf_tbu_clk = {
> + .halt_reg = 0x9d094,
> + .halt_check = BRANCH_HALT_SKIP,
> + .hwcg_reg = 0x9d094,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x62000,
> + .enable_mask = BIT(19),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_ddrss_pcie_sf_tbu_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_disp_hf_axi_clk = {
> + .halt_reg = 0x3700c,
> + .halt_check = BRANCH_HALT_SKIP,
> + .hwcg_reg = 0x3700c,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x3700c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_disp_hf_axi_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_disp_sf_axi_clk = {
> + .halt_reg = 0x37014,
> + .halt_check = BRANCH_HALT_SKIP,
> + .hwcg_reg = 0x37014,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x37014,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_disp_sf_axi_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_eusb3_0_clkref_en = {
> + .halt_reg = 0x9c00c,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x9c00c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_eusb3_0_clkref_en",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_gp1_clk = {
> + .halt_reg = 0x74000,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x74000,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_gp1_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_gp1_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_gp2_clk = {
> + .halt_reg = 0x75000,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x75000,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_gp2_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_gp2_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_gp3_clk = {
> + .halt_reg = 0x76000,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x76000,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_gp3_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_gp3_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_gpu_gpll0_clk_src = {
> + .halt_check = BRANCH_HALT_DELAY,
> + .clkr = {
> + .enable_reg = 0x62000,
> + .enable_mask = BIT(15),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_gpu_gpll0_clk_src",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_gpll0.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
> + .halt_check = BRANCH_HALT_DELAY,
> + .clkr = {
> + .enable_reg = 0x62000,
> + .enable_mask = BIT(16),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_gpu_gpll0_div_clk_src",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_gpll0_out_even.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
> + .halt_reg = 0x81010,
> + .halt_check = BRANCH_HALT_VOTED,
> + .hwcg_reg = 0x81010,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x81010,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_gpu_memnoc_gfx_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
> + .halt_reg = 0x81018,
> + .halt_check = BRANCH_HALT_DELAY,
> + .clkr = {
> + .enable_reg = 0x81018,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_gpu_snoc_dvm_gfx_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie_0_aux_clk = {
> + .halt_reg = 0x7b034,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x62008,
> + .enable_mask = BIT(3),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_pcie_0_aux_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_pcie_0_aux_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
> + .halt_reg = 0x7b030,
> + .halt_check = BRANCH_HALT_VOTED,
> + .hwcg_reg = 0x7b030,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x62008,
> + .enable_mask = BIT(2),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_pcie_0_cfg_ahb_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie_0_clkref_en = {
> + .halt_reg = 0x9c004,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x9c004,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_pcie_0_clkref_en",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
> + .halt_reg = 0x7b028,
> + .halt_check = BRANCH_HALT_SKIP,
> + .clkr = {
> + .enable_reg = 0x62008,
> + .enable_mask = BIT(1),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_pcie_0_mstr_axi_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie_0_phy_rchng_clk = {
> + .halt_reg = 0x7b044,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x62000,
> + .enable_mask = BIT(22),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_pcie_0_phy_rchng_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie_0_pipe_clk = {
> + .halt_reg = 0x7b03c,
> + .halt_check = BRANCH_HALT_SKIP,
> + .clkr = {
> + .enable_reg = 0x62008,
> + .enable_mask = BIT(4),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_pcie_0_pipe_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_pcie_0_pipe_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie_0_slv_axi_clk = {
> + .halt_reg = 0x7b020,
> + .halt_check = BRANCH_HALT_VOTED,
> + .hwcg_reg = 0x7b020,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x62008,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_pcie_0_slv_axi_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
> + .halt_reg = 0x7b01c,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x62008,
> + .enable_mask = BIT(5),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_pcie_0_slv_q2a_axi_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie_1_aux_clk = {
> + .halt_reg = 0x9d030,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x62000,
> + .enable_mask = BIT(29),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_pcie_1_aux_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_pcie_1_aux_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
> + .halt_reg = 0x9d02c,
> + .halt_check = BRANCH_HALT_VOTED,
> + .hwcg_reg = 0x9d02c,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x62000,
> + .enable_mask = BIT(28),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_pcie_1_cfg_ahb_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie_1_clkref_en = {
> + .halt_reg = 0x9c008,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x9c008,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_pcie_1_clkref_en",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
> + .halt_reg = 0x9d024,
> + .halt_check = BRANCH_HALT_SKIP,
> + .clkr = {
> + .enable_reg = 0x62000,
> + .enable_mask = BIT(27),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_pcie_1_mstr_axi_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie_1_phy_aux_clk = {
> + .halt_reg = 0x9d038,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x62000,
> + .enable_mask = BIT(24),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_pcie_1_phy_aux_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_pcie_1_phy_aux_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie_1_phy_rchng_clk = {
> + .halt_reg = 0x9d048,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x62000,
> + .enable_mask = BIT(23),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_pcie_1_phy_rchng_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_pcie_1_phy_rchng_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie_1_pipe_clk = {
> + .halt_reg = 0x9d040,
> + .halt_check = BRANCH_HALT_SKIP,
> + .clkr = {
> + .enable_reg = 0x62000,
> + .enable_mask = BIT(30),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_pcie_1_pipe_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_pcie_1_pipe_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie_1_slv_axi_clk = {
> + .halt_reg = 0x9d01c,
> + .halt_check = BRANCH_HALT_VOTED,
> + .hwcg_reg = 0x9d01c,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x62000,
> + .enable_mask = BIT(26),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_pcie_1_slv_axi_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
> + .halt_reg = 0x9d018,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x62000,
> + .enable_mask = BIT(25),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_pcie_1_slv_q2a_axi_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pdm2_clk = {
> + .halt_reg = 0x4300c,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x4300c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_pdm2_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_pdm2_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pdm_ahb_clk = {
> + .halt_reg = 0x43004,
> + .halt_check = BRANCH_HALT_VOTED,
> + .hwcg_reg = 0x43004,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x43004,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_pdm_ahb_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pdm_xo4_clk = {
> + .halt_reg = 0x43008,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x43008,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_pdm_xo4_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
> + .halt_reg = 0x36008,
> + .halt_check = BRANCH_HALT_VOTED,
> + .hwcg_reg = 0x36008,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x36008,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qmip_camera_nrt_ahb_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
> + .halt_reg = 0x3600c,
> + .halt_check = BRANCH_HALT_VOTED,
> + .hwcg_reg = 0x3600c,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x3600c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qmip_camera_rt_ahb_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qmip_disp_ahb_clk = {
> + .halt_reg = 0x37008,
> + .halt_check = BRANCH_HALT_VOTED,
> + .hwcg_reg = 0x37008,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x37008,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qmip_disp_ahb_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qmip_gpu_ahb_clk = {
> + .halt_reg = 0x81008,
> + .halt_check = BRANCH_HALT_VOTED,
> + .hwcg_reg = 0x81008,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x81008,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qmip_gpu_ahb_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qmip_pcie_ahb_clk = {
> + .halt_reg = 0x7b018,
> + .halt_check = BRANCH_HALT_VOTED,
> + .hwcg_reg = 0x7b018,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x7b018,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qmip_pcie_ahb_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qmip_video_cv_cpu_ahb_clk = {
> + .halt_reg = 0x42014,
> + .halt_check = BRANCH_HALT_VOTED,
> + .hwcg_reg = 0x42014,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x42014,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qmip_video_cv_cpu_ahb_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
> + .halt_reg = 0x42008,
> + .halt_check = BRANCH_HALT_VOTED,
> + .hwcg_reg = 0x42008,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x42008,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qmip_video_cvp_ahb_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qmip_video_v_cpu_ahb_clk = {
> + .halt_reg = 0x42010,
> + .halt_check = BRANCH_HALT_VOTED,
> + .hwcg_reg = 0x42010,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x42010,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qmip_video_v_cpu_ahb_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
> + .halt_reg = 0x4200c,
> + .halt_check = BRANCH_HALT_VOTED,
> + .hwcg_reg = 0x4200c,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x4200c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qmip_video_vcodec_ahb_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
> + .halt_reg = 0x3300c,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x62008,
> + .enable_mask = BIT(9),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qupv3_wrap0_core_2x_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qupv3_wrap0_core_clk = {
> + .halt_reg = 0x33000,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x62008,
> + .enable_mask = BIT(8),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qupv3_wrap0_core_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
> + .halt_reg = 0x2700c,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x62008,
> + .enable_mask = BIT(10),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qupv3_wrap0_s0_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
> + .halt_reg = 0x27140,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x62008,
> + .enable_mask = BIT(11),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qupv3_wrap0_s1_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
> + .halt_reg = 0x27274,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x62008,
> + .enable_mask = BIT(12),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qupv3_wrap0_s2_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
> + .halt_reg = 0x273a8,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x62008,
> + .enable_mask = BIT(13),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qupv3_wrap0_s3_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
> + .halt_reg = 0x274dc,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x62008,
> + .enable_mask = BIT(14),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qupv3_wrap0_s4_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
> + .halt_reg = 0x27610,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x62008,
> + .enable_mask = BIT(15),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qupv3_wrap0_s5_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
> + .halt_reg = 0x27744,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x62008,
> + .enable_mask = BIT(16),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qupv3_wrap0_s6_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
> + .halt_reg = 0x27878,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x62008,
> + .enable_mask = BIT(17),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qupv3_wrap0_s7_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_qupv3_wrap0_s7_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
> + .halt_reg = 0x3314c,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x62008,
> + .enable_mask = BIT(18),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qupv3_wrap1_core_2x_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qupv3_wrap1_core_clk = {
> + .halt_reg = 0x33140,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x62008,
> + .enable_mask = BIT(19),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qupv3_wrap1_core_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
> + .halt_reg = 0x2800c,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x62008,
> + .enable_mask = BIT(22),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qupv3_wrap1_s0_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
> + .halt_reg = 0x28140,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x62008,
> + .enable_mask = BIT(23),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qupv3_wrap1_s1_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
> + .halt_reg = 0x28274,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x62008,
> + .enable_mask = BIT(24),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qupv3_wrap1_s2_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
> + .halt_reg = 0x283a8,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x62008,
> + .enable_mask = BIT(25),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qupv3_wrap1_s3_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
> + .halt_reg = 0x284dc,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x62008,
> + .enable_mask = BIT(26),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qupv3_wrap1_s4_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
> + .halt_reg = 0x28610,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x62008,
> + .enable_mask = BIT(27),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qupv3_wrap1_s5_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
> + .halt_reg = 0x28744,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x62008,
> + .enable_mask = BIT(28),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qupv3_wrap1_s6_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = {
> + .halt_reg = 0x3328c,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x62010,
> + .enable_mask = BIT(3),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qupv3_wrap2_core_2x_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qupv3_wrap2_core_clk = {
> + .halt_reg = 0x33280,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x62010,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qupv3_wrap2_core_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
> + .halt_reg = 0x2e00c,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x62010,
> + .enable_mask = BIT(4),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qupv3_wrap2_s0_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_qupv3_wrap2_s0_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
> + .halt_reg = 0x2e140,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x62010,
> + .enable_mask = BIT(5),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qupv3_wrap2_s1_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_qupv3_wrap2_s1_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
> + .halt_reg = 0x2e274,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x62010,
> + .enable_mask = BIT(6),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qupv3_wrap2_s2_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_qupv3_wrap2_s2_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
> + .halt_reg = 0x2e3a8,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x62010,
> + .enable_mask = BIT(7),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qupv3_wrap2_s3_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_qupv3_wrap2_s3_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
> + .halt_reg = 0x2e4dc,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x62010,
> + .enable_mask = BIT(8),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qupv3_wrap2_s4_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_qupv3_wrap2_s4_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
> + .halt_reg = 0x2e610,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x62010,
> + .enable_mask = BIT(9),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qupv3_wrap2_s5_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_qupv3_wrap2_s5_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qupv3_wrap2_s6_clk = {
> + .halt_reg = 0x2e744,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x62010,
> + .enable_mask = BIT(10),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qupv3_wrap2_s6_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_qupv3_wrap2_s6_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
> + .halt_reg = 0x27004,
> + .halt_check = BRANCH_HALT_VOTED,
> + .hwcg_reg = 0x27004,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x62008,
> + .enable_mask = BIT(6),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qupv3_wrap_0_m_ahb_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
> + .halt_reg = 0x27008,
> + .halt_check = BRANCH_HALT_VOTED,
> + .hwcg_reg = 0x27008,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x62008,
> + .enable_mask = BIT(7),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qupv3_wrap_0_s_ahb_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
> + .halt_reg = 0x28004,
> + .halt_check = BRANCH_HALT_VOTED,
> + .hwcg_reg = 0x28004,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x62008,
> + .enable_mask = BIT(20),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qupv3_wrap_1_m_ahb_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
> + .halt_reg = 0x28008,
> + .halt_check = BRANCH_HALT_VOTED,
> + .hwcg_reg = 0x28008,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x62008,
> + .enable_mask = BIT(21),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qupv3_wrap_1_s_ahb_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
> + .halt_reg = 0x2e004,
> + .halt_check = BRANCH_HALT_VOTED,
> + .hwcg_reg = 0x2e004,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x62010,
> + .enable_mask = BIT(2),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qupv3_wrap_2_m_ahb_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
> + .halt_reg = 0x2e008,
> + .halt_check = BRANCH_HALT_VOTED,
> + .hwcg_reg = 0x2e008,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x62010,
> + .enable_mask = BIT(1),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qupv3_wrap_2_s_ahb_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_sdcc2_ahb_clk = {
> + .halt_reg = 0x2400c,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x2400c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_sdcc2_ahb_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_sdcc2_apps_clk = {
> + .halt_reg = 0x24004,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x24004,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_sdcc2_apps_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_sdcc2_apps_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_sdcc2_at_clk = {
> + .halt_reg = 0x24010,
> + .halt_check = BRANCH_HALT_VOTED,
> + .hwcg_reg = 0x24010,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x24010,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_sdcc2_at_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_sdcc4_ahb_clk = {
> + .halt_reg = 0x2600c,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x2600c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_sdcc4_ahb_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_sdcc4_apps_clk = {
> + .halt_reg = 0x26004,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x26004,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_sdcc4_apps_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_sdcc4_apps_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_sdcc4_at_clk = {
> + .halt_reg = 0x26010,
> + .halt_check = BRANCH_HALT_VOTED,
> + .hwcg_reg = 0x26010,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x26010,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_sdcc4_at_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_ufs_0_clkref_en = {
> + .halt_reg = 0x9c000,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x9c000,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_ufs_0_clkref_en",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_ufs_phy_ahb_clk = {
> + .halt_reg = 0x87020,
> + .halt_check = BRANCH_HALT_VOTED,
> + .hwcg_reg = 0x87020,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x87020,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_ufs_phy_ahb_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_ufs_phy_axi_clk = {
> + .halt_reg = 0x87018,
> + .halt_check = BRANCH_HALT_VOTED,
> + .hwcg_reg = 0x87018,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x87018,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_ufs_phy_axi_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
> + .halt_reg = 0x87018,
> + .halt_check = BRANCH_HALT_VOTED,
> + .hwcg_reg = 0x87018,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x87018,
> + .enable_mask = BIT(1),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_ufs_phy_axi_hw_ctl_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_ufs_phy_ice_core_clk = {
> + .halt_reg = 0x8706c,
> + .halt_check = BRANCH_HALT_VOTED,
> + .hwcg_reg = 0x8706c,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x8706c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_ufs_phy_ice_core_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
> + .halt_reg = 0x8706c,
> + .halt_check = BRANCH_HALT_VOTED,
> + .hwcg_reg = 0x8706c,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x8706c,
> + .enable_mask = BIT(1),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
> + .halt_reg = 0x870a4,
> + .halt_check = BRANCH_HALT_VOTED,
> + .hwcg_reg = 0x870a4,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x870a4,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_ufs_phy_phy_aux_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
> + .halt_reg = 0x870a4,
> + .halt_check = BRANCH_HALT_VOTED,
> + .hwcg_reg = 0x870a4,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x870a4,
> + .enable_mask = BIT(1),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
> + .halt_reg = 0x87028,
> + .halt_check = BRANCH_HALT_DELAY,
> + .clkr = {
> + .enable_reg = 0x87028,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_ufs_phy_rx_symbol_0_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
> + .halt_reg = 0x870c0,
> + .halt_check = BRANCH_HALT_DELAY,
> + .clkr = {
> + .enable_reg = 0x870c0,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_ufs_phy_rx_symbol_1_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
> + .halt_reg = 0x87024,
> + .halt_check = BRANCH_HALT_DELAY,
> + .clkr = {
> + .enable_reg = 0x87024,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_ufs_phy_tx_symbol_0_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
> + .halt_reg = 0x87064,
> + .halt_check = BRANCH_HALT_VOTED,
> + .hwcg_reg = 0x87064,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x87064,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_ufs_phy_unipro_core_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
> + .halt_reg = 0x87064,
> + .halt_check = BRANCH_HALT_VOTED,
> + .hwcg_reg = 0x87064,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x87064,
> + .enable_mask = BIT(1),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_usb30_prim_master_clk = {
> + .halt_reg = 0x49018,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x49018,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_usb30_prim_master_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
> + .halt_reg = 0x49024,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x49024,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_usb30_prim_mock_utmi_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_usb30_prim_sleep_clk = {
> + .halt_reg = 0x49020,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x49020,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_usb30_prim_sleep_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_usb3_0_clkref_en = {
> + .halt_reg = 0x9c010,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x9c010,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_usb3_0_clkref_en",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
> + .halt_reg = 0x4905c,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x4905c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_usb3_prim_phy_aux_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
> + .halt_reg = 0x49060,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x49060,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_usb3_prim_phy_com_aux_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
> + .halt_reg = 0x49064,
> + .halt_check = BRANCH_HALT_DELAY,
> + .hwcg_reg = 0x49064,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x49064,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_usb3_prim_phy_pipe_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_video_axi0_clk = {
> + .halt_reg = 0x42018,
> + .halt_check = BRANCH_HALT_SKIP,
> + .hwcg_reg = 0x42018,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x42018,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_video_axi0_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_video_axi1_clk = {
> + .halt_reg = 0x42020,
> + .halt_check = BRANCH_HALT_SKIP,
> + .hwcg_reg = 0x42020,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x42020,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_video_axi1_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct gdsc pcie_0_gdsc = {
> + .gdscr = 0x7b004,
> + .pd = {
> + .name = "pcie_0_gdsc",
> + },
> + .pwrsts = PWRSTS_OFF_ON,
> +};
> +
> +static struct gdsc pcie_1_gdsc = {
> + .gdscr = 0x9d004,
> + .pd = {
> + .name = "pcie_1_gdsc",
> + },
> + .pwrsts = PWRSTS_OFF_ON,
> +};
> +
> +static struct gdsc ufs_phy_gdsc = {
> + .gdscr = 0x87004,
> + .pd = {
> + .name = "ufs_phy_gdsc",
> + },
> + .pwrsts = PWRSTS_OFF_ON,
> +};
> +
> +static struct gdsc usb30_prim_gdsc = {
> + .gdscr = 0x49004,
> + .pd = {
> + .name = "usb30_prim_gdsc",
> + },
> + .pwrsts = PWRSTS_OFF_ON,
> +};
> +
> +static struct clk_regmap *gcc_sm8450_clocks[] = {
> + [GCC_AGGRE_NOC_PCIE_0_AXI_CLK] = &gcc_aggre_noc_pcie_0_axi_clk.clkr,
> + [GCC_AGGRE_NOC_PCIE_1_AXI_CLK] = &gcc_aggre_noc_pcie_1_axi_clk.clkr,
> + [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
> + [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
> + [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
> + [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
> + [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
> + [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
> + [GCC_CFG_NOC_PCIE_ANOC_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_ahb_clk.clkr,
> + [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
> + [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
> + [GCC_DDRSS_PCIE_SF_TBU_CLK] = &gcc_ddrss_pcie_sf_tbu_clk.clkr,
> + [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
> + [GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr,
> + [GCC_EUSB3_0_CLKREF_EN] = &gcc_eusb3_0_clkref_en.clkr,
> + [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
> + [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
> + [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
> + [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
> + [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
> + [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
> + [GCC_GPLL0] = &gcc_gpll0.clkr,
> + [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
> + [GCC_GPLL4] = &gcc_gpll4.clkr,
> + [GCC_GPLL9] = &gcc_gpll9.clkr,
> + [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
> + [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
> + [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
> + [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
> + [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
> + [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
> + [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
> + [GCC_PCIE_0_CLKREF_EN] = &gcc_pcie_0_clkref_en.clkr,
> + [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
> + [GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr,
> + [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr,
> + [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
> + [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr,
> + [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
> + [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
> + [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
> + [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
> + [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
> + [GCC_PCIE_1_CLKREF_EN] = &gcc_pcie_1_clkref_en.clkr,
> + [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
> + [GCC_PCIE_1_PHY_AUX_CLK] = &gcc_pcie_1_phy_aux_clk.clkr,
> + [GCC_PCIE_1_PHY_AUX_CLK_SRC] = &gcc_pcie_1_phy_aux_clk_src.clkr,
> + [GCC_PCIE_1_PHY_RCHNG_CLK] = &gcc_pcie_1_phy_rchng_clk.clkr,
> + [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr,
> + [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
> + [GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr,
> + [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
> + [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
> + [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
> + [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
> + [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
> + [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
> + [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
> + [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
> + [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
> + [GCC_QMIP_GPU_AHB_CLK] = &gcc_qmip_gpu_ahb_clk.clkr,
> + [GCC_QMIP_PCIE_AHB_CLK] = &gcc_qmip_pcie_ahb_clk.clkr,
> + [GCC_QMIP_VIDEO_CV_CPU_AHB_CLK] = &gcc_qmip_video_cv_cpu_ahb_clk.clkr,
> + [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
> + [GCC_QMIP_VIDEO_V_CPU_AHB_CLK] = &gcc_qmip_video_v_cpu_ahb_clk.clkr,
> + [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
> + [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
> + [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
> + [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
> + [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
> + [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
> + [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
> + [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
> + [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
> + [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
> + [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
> + [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
> + [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
> + [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
> + [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
> + [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
> + [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
> + [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
> + [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
> + [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
> + [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
> + [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
> + [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
> + [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
> + [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
> + [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
> + [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
> + [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
> + [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
> + [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
> + [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
> + [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
> + [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
> + [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
> + [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
> + [GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr,
> + [GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr,
> + [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
> + [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
> + [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
> + [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
> + [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
> + [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
> + [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
> + [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
> + [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
> + [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
> + [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
> + [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
> + [GCC_QUPV3_WRAP2_S6_CLK] = &gcc_qupv3_wrap2_s6_clk.clkr,
> + [GCC_QUPV3_WRAP2_S6_CLK_SRC] = &gcc_qupv3_wrap2_s6_clk_src.clkr,
> + [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
> + [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
> + [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
> + [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
> + [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
> + [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
> + [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
> + [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
> + [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
> + [GCC_SDCC2_AT_CLK] = &gcc_sdcc2_at_clk.clkr,
> + [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
> + [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
> + [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
> + [GCC_SDCC4_AT_CLK] = &gcc_sdcc4_at_clk.clkr,
> + [GCC_UFS_0_CLKREF_EN] = &gcc_ufs_0_clkref_en.clkr,
> + [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
> + [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
> + [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
> + [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
> + [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
> + [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
> + [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
> + [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
> + [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
> + [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
> + [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
> + [GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr,
> + [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
> + [GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr,
> + [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
> + [GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr,
> + [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
> + [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,
> + [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
> + [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
> + [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
> + [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
> + [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,
> + [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
> + [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
> + [GCC_USB3_0_CLKREF_EN] = &gcc_usb3_0_clkref_en.clkr,
> + [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
> + [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
> + [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
> + [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
> + [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,
> + [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
> + [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
> +};
> +
> +static const struct qcom_reset_map gcc_sm8450_resets[] = {
> + [GCC_CAMERA_BCR] = { 0x36000 },
> + [GCC_DISPLAY_BCR] = { 0x37000 },
> + [GCC_GPU_BCR] = { 0x81000 },
> + [GCC_PCIE_0_BCR] = { 0x7b000 },
> + [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x7c014 },
> + [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x7c020 },
> + [GCC_PCIE_0_PHY_BCR] = { 0x7c01c },
> + [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x7c028 },
> + [GCC_PCIE_1_BCR] = { 0x9d000 },
> + [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x9e014 },
> + [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x9e020 },
> + [GCC_PCIE_1_PHY_BCR] = { 0x9e01c },
> + [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x9e000 },
> + [GCC_PCIE_PHY_BCR] = { 0x7f000 },
> + [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x7f00c },
> + [GCC_PCIE_PHY_COM_BCR] = { 0x7f010 },
> + [GCC_PDM_BCR] = { 0x43000 },
> + [GCC_QUPV3_WRAPPER_0_BCR] = { 0x27000 },
> + [GCC_QUPV3_WRAPPER_1_BCR] = { 0x28000 },
> + [GCC_QUPV3_WRAPPER_2_BCR] = { 0x2e000 },
> + [GCC_QUSB2PHY_PRIM_BCR] = { 0x22000 },
> + [GCC_QUSB2PHY_SEC_BCR] = { 0x22004 },
> + [GCC_SDCC2_BCR] = { 0x24000 },
> + [GCC_SDCC4_BCR] = { 0x26000 },
> + [GCC_UFS_PHY_BCR] = { 0x87000 },
> + [GCC_USB30_PRIM_BCR] = { 0x49000 },
> + [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x60008 },
> + [GCC_USB3_DP_PHY_SEC_BCR] = { 0x60014 },
> + [GCC_USB3_PHY_PRIM_BCR] = { 0x60000 },
> + [GCC_USB3_PHY_SEC_BCR] = { 0x6000c },
> + [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x60004 },
> + [GCC_USB3PHY_PHY_SEC_BCR] = { 0x60010 },
> + [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x7a000 },
> + [GCC_VIDEO_AXI0_CLK_ARES] = { 0x42018, 2 },
> + [GCC_VIDEO_AXI1_CLK_ARES] = { 0x42020, 2 },
> + [GCC_VIDEO_BCR] = { 0x42000 },
> +};
> +
> +static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
> + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
> + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
> + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
> + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
> + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
> + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
> + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
> + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
> + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
> + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
> + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
> + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
> + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
> + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
> + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),
> + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src),
> + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src),
> + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src),
> + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src),
> + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src),
> + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src),
> + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s6_clk_src),
> +};
> +
> +static struct gdsc *gcc_sm8450_gdscs[] = {
> + [PCIE_0_GDSC] = &pcie_0_gdsc,
> + [PCIE_1_GDSC] = &pcie_1_gdsc,
> + [UFS_PHY_GDSC] = &ufs_phy_gdsc,
> + [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
> +};
> +
> +static const struct regmap_config gcc_sm8450_regmap_config = {
> + .reg_bits = 32,
> + .reg_stride = 4,
> + .val_bits = 32,
> + .max_register = 0x1f1030,
> + .fast_io = true,
> +};
> +
> +static const struct qcom_cc_desc gcc_sm8450_desc = {
> + .config = &gcc_sm8450_regmap_config,
> + .clks = gcc_sm8450_clocks,
> + .num_clks = ARRAY_SIZE(gcc_sm8450_clocks),
> + .resets = gcc_sm8450_resets,
> + .num_resets = ARRAY_SIZE(gcc_sm8450_resets),
> + .gdscs = gcc_sm8450_gdscs,
> + .num_gdscs = ARRAY_SIZE(gcc_sm8450_gdscs),
> +};
> +
> +static const struct of_device_id gcc_sm8450_match_table[] = {
> + { .compatible = "qcom,gcc-sm8450" },
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, gcc_sm8450_match_table);
> +
> +static int gcc_sm8450_probe(struct platform_device *pdev)
> +{
> + struct regmap *regmap;
> + int ret;
> +
> + regmap = qcom_cc_map(pdev, &gcc_sm8450_desc);
> + if (IS_ERR(regmap))
> + return PTR_ERR(regmap);
> +
> + ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
> + ARRAY_SIZE(gcc_dfs_clocks));
> + if (ret)
> + return ret;
> +
> + /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
> + regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14));
> +
> + /* Keep the critical clock always-On
> + * gcc_camera_ahb_clk, gcc_camera_xo_clk, gcc_disp_ahb_clk,
> + * gcc_disp_xo_clk, gcc_gpu_cfg_ahb_clk, gcc_video_ahb_clk,
> + * gcc_video_xo_clk
> + */
> + regmap_update_bits(regmap, 0x36004, BIT(0), BIT(0));
> + regmap_update_bits(regmap, 0x36020, BIT(0), BIT(0));
> + regmap_update_bits(regmap, 0x37004, BIT(0), BIT(0));
> + regmap_update_bits(regmap, 0x3701c, BIT(0), BIT(0));
> + regmap_update_bits(regmap, 0x81004, BIT(0), BIT(0));
> + regmap_update_bits(regmap, 0x42004, BIT(0), BIT(0));
> + regmap_update_bits(regmap, 0x42028, BIT(0), BIT(0));
> +
> + ret = qcom_cc_really_probe(pdev, &gcc_sm8450_desc, regmap);
> + if (ret) {
> + dev_err(&pdev->dev, "Failed to register GCC clocks\n");
> + return ret;
> + }
> +
> + dev_info(&pdev->dev, "Registered GCC clocks\n");
> +
> + return ret;
> +}
> +
> +static struct platform_driver gcc_sm8450_driver = {
> + .probe = gcc_sm8450_probe,
> + .driver = {
> + .name = "gcc-sm8450",
> + .of_match_table = gcc_sm8450_match_table,
> + },
> +};
> +
> +static int __init gcc_sm8450_init(void)
> +{
> + return platform_driver_register(&gcc_sm8450_driver);
> +}
> +subsys_initcall(gcc_sm8450_init);
> +
> +static void __exit gcc_sm8450_exit(void)
> +{
> + platform_driver_unregister(&gcc_sm8450_driver);
> +}
> +module_exit(gcc_sm8450_exit);
> +
> +MODULE_DESCRIPTION("QTI GCC SM8450 Driver");
> +MODULE_LICENSE("GPL v2");
>
--
With best wishes
Dmitry
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