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Message-ID: <20211201155128.sasoiv3awjcfrjhw@SoMainline.org>
Date: Wed, 1 Dec 2021 16:51:28 +0100
From: Marijn Suijten <marijn.suijten@...ainline.org>
To: Martin Botka <martin.botka@...ainline.org>
Cc: martin.botka1@...il.com, ~postmarketos/upstreaming@...ts.sr.ht,
konrad.dybcio@...ainline.org,
angelogioacchino.delregno@...ainline.org,
jamipkettunen@...ainline.org, paul.bouchara@...ainline.org,
Andy Gross <agross@...nel.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 3/3] arm64: dt: qcom: sm6125.dtsi: Add dispcc
On 2021-11-30 22:21:34, Martin Botka wrote:
> Add the dispcc node from the newly added DISPCC
> driver for Qualcomm Technology Inc's SM6125 SoC.
>
> Signed-off-by: Martin Botka <martin.botka@...ainline.org>
> ---
> arch/arm64/boot/dts/qcom/sm6125.dtsi | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
> index 51286ddbdb10..78f4705e4117 100644
> --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
> @@ -3,6 +3,7 @@
> * Copyright (c) 2021, Martin Botka <martin.botka@...ainline.org>
> */
>
> +#include <dt-bindings/clock/qcom,dispcc-sm6125.h>
> #include <dt-bindings/clock/qcom,gcc-sm6125.h>
> #include <dt-bindings/clock/qcom,rpmcc.h>
> #include <dt-bindings/gpio/gpio.h>
> @@ -317,6 +318,17 @@ soc {
> ranges = <0x00 0x00 0x00 0xffffffff>;
> compatible = "simple-bus";
>
> + dispcc: clock-controller@...0000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "qcom,dispcc-sm6125";
> + reg = <0x5f00000 0x20000>;
> + clocks = <&gcc GCC_DISP_AHB_CLK>;
> + clock-names = "cfg_ahb_clk";
It looks like this lacks all the clocks that are supposedly required as
per the yaml DT bindings provided in patch 1/3 - should those be added
and set to `<0>` where unavailable, otherwise dtbs_check may not pass?
> + #clock-cells = <1>;
> + #power-domain-cells = <1>;
> + };
> +
> tcsr_mutex: hwlock@...000 {
> compatible = "qcom,tcsr-mutex";
> reg = <0x00340000 0x20000>;
> --
> 2.34.0
>
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