| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <20211201154642.24j5emibojfel2vr@SoMainline.org>
Date: Wed, 1 Dec 2021 16:46:42 +0100
From: Marijn Suijten <marijn.suijten@...ainline.org>
To: Martin Botka <martin.botka@...ainline.org>
Cc: martin.botka1@...il.com, ~postmarketos/upstreaming@...ts.sr.ht,
konrad.dybcio@...ainline.org,
angelogioacchino.delregno@...ainline.org,
jamipkettunen@...ainline.org, paul.bouchara@...ainline.org,
Andy Gross <agross@...nel.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/3] clk: qcom: Add display clock controller driver for
SM6125
On 2021-11-30 22:21:33, Martin Botka wrote:
> Add support for the display clock controller found on SM6125
> based devices. This allows display drivers to probe and
> control their clocks.
>
> Signed-off-by: Martin Botka <martin.botka@...ainline.org>
This got lost in the pipeline:
Reviewed-by: Marijn Suijten <marijn.suijten@...ainline.org>
> ---
> drivers/clk/qcom/Kconfig | 9 +
> drivers/clk/qcom/Makefile | 1 +
> drivers/clk/qcom/dispcc-sm6125.c | 710 +++++++++++++++++++++++++++++++
> 3 files changed, 720 insertions(+)
> create mode 100644 drivers/clk/qcom/dispcc-sm6125.c
>
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 74efc82127e1..2399b45767f5 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -564,6 +564,15 @@ config SM_CAMCC_8250
> Support for the camera clock controller on SM8250 devices.
> Say Y if you want to support camera devices and camera functionality.
>
> +config SM_DISPCC_6125
> + tristate "SM6125 Display Clock Controller"
> + depends on SM_GCC_6125
> + help
> + Support for the display clock controller on Qualcomm Technologies, Inc
> + SM6125 devices.
> + Say Y if you want to support display devices and functionality such as
> + splash screen
> +
> config SM_DISPCC_8250
> tristate "SM8150 and SM8250 Display Clock Controller"
> depends on SM_GCC_8150 || SM_GCC_8250
> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> index 1718c34d3551..c9f38fbf86a8 100644
> --- a/drivers/clk/qcom/Makefile
> +++ b/drivers/clk/qcom/Makefile
> @@ -83,6 +83,7 @@ obj-$(CONFIG_SDM_LPASSCC_845) += lpasscc-sdm845.o
> obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
> obj-$(CONFIG_SDX_GCC_55) += gcc-sdx55.o
> obj-$(CONFIG_SM_CAMCC_8250) += camcc-sm8250.o
> +obj-$(CONFIG_SM_DISPCC_6125) += dispcc-sm6125.o
> obj-$(CONFIG_SM_DISPCC_8250) += dispcc-sm8250.o
> obj-$(CONFIG_SM_GCC_6115) += gcc-sm6115.o
> obj-$(CONFIG_SM_GCC_6125) += gcc-sm6125.o
> diff --git a/drivers/clk/qcom/dispcc-sm6125.c b/drivers/clk/qcom/dispcc-sm6125.c
> new file mode 100644
> index 000000000000..dbab92d6261f
> --- /dev/null
> +++ b/drivers/clk/qcom/dispcc-sm6125.c
> @@ -0,0 +1,710 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021, The Linux Foundation. All rights reserved.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +
> +#include <dt-bindings/clock/qcom,dispcc-sm6125.h>
> +
> +#include "clk-alpha-pll.h"
> +#include "clk-branch.h"
> +#include "clk-rcg.h"
> +#include "clk-regmap.h"
> +#include "common.h"
> +#include "gdsc.h"
> +
> +enum {
> + P_BI_TCXO,
> + P_DISP_CC_PLL0_OUT_MAIN,
> + P_DP_PHY_PLL_LINK_CLK,
> + P_DP_PHY_PLL_VCO_DIV_CLK,
> + P_DSI0_PHY_PLL_OUT_BYTECLK,
> + P_DSI0_PHY_PLL_OUT_DSICLK,
> + P_DSI1_PHY_PLL_OUT_DSICLK,
> + P_GPLL0_OUT_MAIN,
> +};
> +
> +static struct pll_vco disp_cc_pll_vco[] = {
> + { 500000000, 1000000000, 2 },
> +};
> +
> +static struct clk_alpha_pll disp_cc_pll0 = {
> + .offset = 0x0,
> + .vco_table = disp_cc_pll_vco,
> + .num_vco = ARRAY_SIZE(disp_cc_pll_vco),
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> + .flags = SUPPORTS_DYNAMIC_UPDATE,
> + .clkr = {
> + .hw.init = &(struct clk_init_data){
> + .name = "disp_cc_pll0",
> + .parent_data = &(const struct clk_parent_data){
> + .fw_name = "bi_tcxo",
> + },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_ops,
> + },
> + },
> +};
> +
> +/* 768MHz configuration */
> +static const struct alpha_pll_config disp_cc_pll0_config = {
> + .l = 0x28,
> + .vco_val = 0x2 << 20,
> + .vco_mask = 0x3 << 20,
> + .main_output_mask = BIT(0),
> + .config_ctl_val = 0x4001055b,
> +};
> +
> +static const struct parent_map disp_cc_parent_map_0[] = {
> + { P_BI_TCXO, 0 },
> +};
> +
> +static const struct clk_parent_data disp_cc_parent_data_0[] = {
> + { .fw_name = "bi_tcxo" },
> +};
> +
> +static const struct parent_map disp_cc_parent_map_1[] = {
> + { P_BI_TCXO, 0 },
> + { P_DP_PHY_PLL_LINK_CLK, 1 },
> + { P_DP_PHY_PLL_VCO_DIV_CLK, 2 },
> +};
> +
> +static const struct clk_parent_data disp_cc_parent_data_1[] = {
> + { .fw_name = "bi_tcxo" },
> + { .fw_name = "dp_phy_pll_link_clk" },
> + { .fw_name = "dp_phy_pll_vco_div_clk" },
> +};
> +
> +static const struct parent_map disp_cc_parent_map_2[] = {
> + { P_BI_TCXO, 0 },
> + { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
> +};
> +
> +static const struct clk_parent_data disp_cc_parent_data_2[] = {
> + { .fw_name = "bi_tcxo" },
> + { .fw_name = "dsi0_phy_pll_out_byteclk" },
> +};
> +
> +static const struct parent_map disp_cc_parent_map_3[] = {
> + { P_BI_TCXO, 0 },
> + { P_DISP_CC_PLL0_OUT_MAIN, 1 },
> + { P_GPLL0_OUT_MAIN, 4 },
> +};
> +
> +static const struct clk_parent_data disp_cc_parent_data_3[] = {
> + { .fw_name = "bi_tcxo" },
> + { .hw = &disp_cc_pll0.clkr.hw },
> + { .fw_name = "gcc_disp_gpll0_div_clk_src" },
> +};
> +
> +static const struct parent_map disp_cc_parent_map_4[] = {
> + { P_BI_TCXO, 0 },
> + { P_GPLL0_OUT_MAIN, 4 },
> +};
> +
> +static const struct clk_parent_data disp_cc_parent_data_4[] = {
> + { .fw_name = "bi_tcxo" },
> + { .fw_name = "gcc_disp_gpll0_div_clk_src" },
> +};
> +
> +static const struct parent_map disp_cc_parent_map_5[] = {
> + { P_BI_TCXO, 0 },
> + { P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
> + { P_DSI1_PHY_PLL_OUT_DSICLK, 2 },
> +};
> +
> +static const struct clk_parent_data disp_cc_parent_data_5[] = {
> + { .fw_name = "bi_tcxo" },
> + { .fw_name = "dsi0_phy_pll_out_dsiclk" },
> + { .fw_name = "dsi1_phy_pll_out_dsiclk" },
> +};
> +
> +static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
> + F(19200000, P_BI_TCXO, 1, 0, 0),
> + F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),
> + F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
> + .cmd_rcgr = 0x2154,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = disp_cc_parent_map_4,
> + .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "disp_cc_mdss_ahb_clk_src",
> + .parent_data = disp_cc_parent_data_4,
> + .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
> + .cmd_rcgr = 0x20bc,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = disp_cc_parent_map_2,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "disp_cc_mdss_byte0_clk_src",
> + .parent_data = disp_cc_parent_data_2,
> + .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
> + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
> + .ops = &clk_byte2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux1_clk_src[] = {
> + F(19200000, P_BI_TCXO, 1, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
> + .cmd_rcgr = 0x213c,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = disp_cc_parent_map_0,
> + .freq_tbl = ftbl_disp_cc_mdss_dp_aux1_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "disp_cc_mdss_dp_aux_clk_src",
> + .parent_data = disp_cc_parent_data_0,
> + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_disp_cc_mdss_dp_crypto_clk_src[] = {
> + F( 180000, P_DP_PHY_PLL_LINK_CLK, 1.5, 0, 0),
> + F( 360000, P_DP_PHY_PLL_LINK_CLK, 1.5, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {
> + .cmd_rcgr = 0x210c,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = disp_cc_parent_map_1,
> + .freq_tbl = ftbl_disp_cc_mdss_dp_crypto_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "disp_cc_mdss_dp_crypto_clk_src",
> + .parent_data = disp_cc_parent_data_1,
> + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
> + .flags = CLK_GET_RATE_NOCACHE,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] = {
> + F( 162000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
> + F( 270000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
> + F( 540000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
> + .cmd_rcgr = 0x20f0,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = disp_cc_parent_map_1,
> + .freq_tbl = ftbl_disp_cc_mdss_dp_link_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "disp_cc_mdss_dp_link_clk_src",
> + .parent_data = disp_cc_parent_data_1,
> + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
> + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
> + .cmd_rcgr = 0x2124,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = disp_cc_parent_map_1,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "disp_cc_mdss_dp_pixel_clk_src",
> + .parent_data = disp_cc_parent_data_1,
> + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
> + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
> + .ops = &clk_dp_ops,
> + },
> +};
> +
> +static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
> + .cmd_rcgr = 0x20d8,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = disp_cc_parent_map_2,
> + .freq_tbl = ftbl_disp_cc_mdss_dp_aux1_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "disp_cc_mdss_esc0_clk_src",
> + .parent_data = disp_cc_parent_data_2,
> + .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
> + F(19200000, P_BI_TCXO, 1, 0, 0),
> + F(192000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
> + F(256000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
> + F(307200000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
> + F(384000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
> + F(400000000, P_GPLL0_OUT_MAIN, 1.5, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
> + .cmd_rcgr = 0x2074,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = disp_cc_parent_map_3,
> + .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "disp_cc_mdss_mdp_clk_src",
> + .parent_data = disp_cc_parent_data_3,
> + .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
> + .cmd_rcgr = 0x205c,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = disp_cc_parent_map_5,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "disp_cc_mdss_pclk0_clk_src",
> + .parent_data = disp_cc_parent_data_5,
> + .num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
> + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
> + .ops = &clk_pixel_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = {
> + F(19200000, P_BI_TCXO, 1, 0, 0),
> + F(192000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
> + F(256000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
> + F(307200000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
> + .cmd_rcgr = 0x208c,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = disp_cc_parent_map_3,
> + .freq_tbl = ftbl_disp_cc_mdss_rot_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "disp_cc_mdss_rot_clk_src",
> + .parent_data = disp_cc_parent_data_3,
> + .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
> + .cmd_rcgr = 0x20a4,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = disp_cc_parent_map_0,
> + .freq_tbl = ftbl_disp_cc_mdss_dp_aux1_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "disp_cc_mdss_vsync_clk_src",
> + .parent_data = disp_cc_parent_data_0,
> + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_branch disp_cc_mdss_ahb_clk = {
> + .halt_reg = 0x2044,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x2044,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "disp_cc_mdss_ahb_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &disp_cc_mdss_ahb_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch disp_cc_mdss_byte0_clk = {
> + .halt_reg = 0x2024,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x2024,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "disp_cc_mdss_byte0_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &disp_cc_mdss_byte0_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
> + .halt_reg = 0x2028,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x2028,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "disp_cc_mdss_byte0_intf_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &disp_cc_mdss_byte0_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_GET_RATE_NOCACHE,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch disp_cc_mdss_dp_aux_clk = {
> + .halt_reg = 0x2040,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x2040,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "disp_cc_mdss_dp_aux_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &disp_cc_mdss_dp_aux_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch disp_cc_mdss_dp_crypto_clk = {
> + .halt_reg = 0x2038,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x2038,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "disp_cc_mdss_dp_crypto_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &disp_cc_mdss_dp_crypto_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch disp_cc_mdss_dp_link_clk = {
> + .halt_reg = 0x2030,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x2030,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "disp_cc_mdss_dp_link_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &disp_cc_mdss_dp_link_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch disp_cc_mdss_dp_link_intf_clk = {
> + .halt_reg = 0x2034,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x2034,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "disp_cc_mdss_dp_link_intf_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &disp_cc_mdss_dp_link_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_GET_RATE_NOCACHE,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch disp_cc_mdss_dp_pixel_clk = {
> + .halt_reg = 0x203c,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x203c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "disp_cc_mdss_dp_pixel_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &disp_cc_mdss_dp_pixel_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch disp_cc_mdss_esc0_clk = {
> + .halt_reg = 0x202c,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x202c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "disp_cc_mdss_esc0_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &disp_cc_mdss_esc0_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch disp_cc_mdss_mdp_clk = {
> + .halt_reg = 0x2008,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x2008,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "disp_cc_mdss_mdp_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &disp_cc_mdss_mdp_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
> + .halt_reg = 0x2018,
> + .halt_check = BRANCH_VOTED,
> + .clkr = {
> + .enable_reg = 0x2018,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "disp_cc_mdss_mdp_lut_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &disp_cc_mdss_mdp_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
> + .halt_reg = 0x4004,
> + .halt_check = BRANCH_VOTED,
> + .clkr = {
> + .enable_reg = 0x4004,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "disp_cc_mdss_non_gdsc_ahb_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &disp_cc_mdss_ahb_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch disp_cc_mdss_pclk0_clk = {
> + .halt_reg = 0x2004,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x2004,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "disp_cc_mdss_pclk0_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &disp_cc_mdss_pclk0_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch disp_cc_mdss_rot_clk = {
> + .halt_reg = 0x2010,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x2010,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "disp_cc_mdss_rot_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &disp_cc_mdss_rot_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch disp_cc_mdss_vsync_clk = {
> + .halt_reg = 0x2020,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x2020,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "disp_cc_mdss_vsync_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &disp_cc_mdss_vsync_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch disp_cc_xo_clk = {
> + .halt_reg = 0x604c,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x604c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "disp_cc_xo_clk",
> + .flags = CLK_IS_CRITICAL,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct gdsc mdss_gdsc = {
> + .gdscr = 0x3000,
> + .pd = {
> + .name = "mdss_gdsc",
> + },
> + .pwrsts = PWRSTS_OFF_ON,
> + .flags = HW_CTRL,
> +};
> +
> +static struct clk_regmap *disp_cc_sm6125_clocks[] = {
> + [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
> + [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
> + [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
> + [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
> + [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
> + [DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr,
> + [DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr,
> + [DISP_CC_MDSS_DP_CRYPTO_CLK] = &disp_cc_mdss_dp_crypto_clk.clkr,
> + [DISP_CC_MDSS_DP_CRYPTO_CLK_SRC] = &disp_cc_mdss_dp_crypto_clk_src.clkr,
> + [DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr,
> + [DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr,
> + [DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr,
> + [DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr,
> + [DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr,
> + [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
> + [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
> + [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
> + [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
> + [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
> + [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
> + [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
> + [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
> + [DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
> + [DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
> + [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
> + [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
> + [DISP_CC_PLL0] = &disp_cc_pll0.clkr,
> + [DISP_CC_XO_CLK] = &disp_cc_xo_clk.clkr,
> +};
> +
> +static struct gdsc *disp_cc_sm6125_gdscs[] = {
> + [MDSS_GDSC] = &mdss_gdsc,
> +};
> +
> +static const struct regmap_config disp_cc_sm6125_regmap_config = {
> + .reg_bits = 32,
> + .reg_stride = 4,
> + .val_bits = 32,
> + .max_register = 0x10000,
> + .fast_io = true,
> +};
> +
> +static const struct qcom_cc_desc disp_cc_sm6125_desc = {
> + .config = &disp_cc_sm6125_regmap_config,
> + .clks = disp_cc_sm6125_clocks,
> + .num_clks = ARRAY_SIZE(disp_cc_sm6125_clocks),
> + .gdscs = disp_cc_sm6125_gdscs,
> + .num_gdscs = ARRAY_SIZE(disp_cc_sm6125_gdscs),
> +};
> +
> +static const struct of_device_id disp_cc_sm6125_match_table[] = {
> + { .compatible = "qcom,dispcc-sm6125" },
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, disp_cc_sm6125_match_table);
> +
> +static int disp_cc_sm6125_probe(struct platform_device *pdev)
> +{
> + struct regmap *regmap;
> +
> + regmap = qcom_cc_map(pdev, &disp_cc_sm6125_desc);
> + if (IS_ERR(regmap))
> + return PTR_ERR(regmap);
> +
> + clk_alpha_pll_configure(&disp_cc_pll0, regmap,
> + &disp_cc_pll0_config);
> +
> + return qcom_cc_really_probe(pdev, &disp_cc_sm6125_desc, regmap);
> +}
> +
> +static struct platform_driver disp_cc_sm6125_driver = {
> + .probe = disp_cc_sm6125_probe,
> + .driver = {
> + .name = "disp_cc-sm6125",
> + .of_match_table = disp_cc_sm6125_match_table,
> + },
> +};
> +
> +static int __init disp_cc_sm6125_init(void)
> +{
> + return platform_driver_register(&disp_cc_sm6125_driver);
> +}
> +subsys_initcall(disp_cc_sm6125_init);
> +
> +static void __exit disp_cc_sm6125_exit(void)
> +{
> + platform_driver_unregister(&disp_cc_sm6125_driver);
> +}
> +module_exit(disp_cc_sm6125_exit);
> +
> +MODULE_DESCRIPTION("QTI DISPCC SM6125 Driver");
> +MODULE_LICENSE("GPL v2");
> --
> 2.34.0
>
Powered by blists - more mailing lists