linux-kernel - [PATCH v2 1/4] dt-bindings: pci: layerscape-pci: Add a optional property big-endian

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Message-Id: <20211202004636.5276-2-leoyang.li@nxp.com>
Date:   Wed,  1 Dec 2021 18:46:33 -0600
From:   Li Yang <leoyang.li@....com>
To:     Bjorn Helgaas <bhelgaas@...gle.com>,
        Rob Herring <robh+dt@...nel.org>, linux-pci@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        Hou Zhiqiang <Zhiqiang.Hou@....com>
Cc:     Rob Herring <robh@...nel.org>
Subject: [PATCH v2 1/4] dt-bindings: pci: layerscape-pci: Add a optional property big-endian

From: Hou Zhiqiang <Zhiqiang.Hou@....com>

This property is to indicate the endianness when accessing the
PEX_LUT and PF register block, so if these registers are
implemented in big-endian, specify this property.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@....com>
Acked-by: Rob Herring <robh@...nel.org>
---
 Documentation/devicetree/bindings/pci/layerscape-pci.txt | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
index f36efa73a470..215d2ee65c83 100644
--- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
@@ -40,6 +40,10 @@ Required properties:
   of the data transferred from/to the IP block. This can avoid the software
   cache flush/invalid actions, and improve the performance significantly.
 
+Optional properties:
+- big-endian: If the PEX_LUT and PF register block is in big-endian, specify
+  this property.
+
 Example:
 
 	pcie@...0000 {
-- 
2.25.1