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Message-Id: <20211202004636.5276-3-leoyang.li@nxp.com>
Date: Wed, 1 Dec 2021 18:46:34 -0600
From: Li Yang <leoyang.li@....com>
To: Bjorn Helgaas <bhelgaas@...gle.com>,
Rob Herring <robh+dt@...nel.org>, linux-pci@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Hou Zhiqiang <Zhiqiang.Hou@....com>
Cc: Rob Herring <robh@...nel.org>
Subject: [PATCH v2 2/4] dt-bindings: pci: layerscape-pci: Update the description of SCFG property
From: Hou Zhiqiang <Zhiqiang.Hou@....com>
Update the description of the second entry of 'fsl,pcie-scfg' property,
as the LS1043A PCIe controller also has some control registers in SCFG
block, while it has 3 controllers.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@....com>
Acked-by: Rob Herring <robh@...nel.org>
---
Documentation/devicetree/bindings/pci/layerscape-pci.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
index 215d2ee65c83..f1115fcd8088 100644
--- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
@@ -34,7 +34,7 @@ Required properties:
"intr": The interrupt that is asserted for controller interrupts
- fsl,pcie-scfg: Must include two entries.
The first entry must be a link to the SCFG device node
- The second entry must be '0' or '1' based on physical PCIe controller index.
+ The second entry is the physical PCIe controller index starting from '0'.
This is used to get SCFG PEXN registers
- dma-coherent: Indicates that the hardware IP block can ensure the coherency
of the data transferred from/to the IP block. This can avoid the software
--
2.25.1
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