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Date:   Thu, 2 Dec 2021 12:48:55 +0100
From:   Herve Codina <herve.codina@...tlin.com>
To:     Viresh Kumar <viresh.kumar@...aro.org>
Cc:     Viresh Kumar <vireshk@...nel.org>,
        Shiraz Hashim <shiraz.linux.kernel@...il.com>, soc@...nel.org,
        Rob Herring <robh+dt@...nel.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Marc Zyngier <maz@...nel.org>,
        Linus Walleij <linus.walleij@...aro.org>,
        linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-gpio@...r.kernel.org,
        Thomas Petazzoni <thomas.petazzoni@...tlin.com>
Subject: Re: [PATCH 0/6] spear: Fix SPEAr3XX plgpio support

On Thu, 2 Dec 2021 16:57:00 +0530
Viresh Kumar <viresh.kumar@...aro.org> wrote:

> On 02-12-21, 10:52, Herve Codina wrote:
> > Hi,
> > 
> > This patch series fixes the plgpio support on SPEAr3xx SOCs.
> > 
> > The first four patches of this series fixes a ressources
> > sharing issue between the plgpio driver and the pinmux
> > driver.
> > Indeed, these two drivers can use the same IO address range
> > on some SPEAr3xx SOCs.
> > To solve the issue, a regmap (syscon managed) is used in both
> > drivers and the plgpio driver can reference the pinmux regmap
> > to use it.
> > 
> > The second part of this series is related to IRQs.
> > The plgpio on SPEAr320s SOC uses an IRQ line in the reserve
> > range (from SPEAr320 point of view).
> > This issue is fixed enabling all the 'reserved' IRQs and
> > adding a dtsi file for the SPEAr320s with the correct interrupt
> > for the plgpio node.  
> 
> Are these changes backwards compatible ? I mean new kernel will work
> with old DTBs ? It may be quite important to not break that here.
> 

Yes they are.
- the regmap reference (phandle) is optional.
- The IRQ for plgpio is used only on the new spear320s.dtsi.

I have not seen any issues on my board (spear320s SOC) when I only add support
for the 'reserved' IRQs (ie no spurious interrupts occur when I apply the patch
related to shirq).
I cannot test on SPEAr320 SOC as I haven't got any board with this SOC.

Herve

-- 
Hervé Codina, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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