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Message-ID: <20211206164409.oua5i77odmzmaqfs@notapiano>
Date: Mon, 6 Dec 2021 11:44:09 -0500
From: Nícolas F. R. A. Prado
<nfraprado@...labora.com>
To: Chun-Jie Chen <chun-jie.chen@...iatek.com>
Cc: Matthias Brugger <matthias.bgg@...il.com>,
Rob Herring <robh+dt@...nel.org>,
Nicolas Boichat <drinkcat@...omium.org>,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, linux-mediatek@...ts.infradead.org,
srv_heupstream@...iatek.com,
Project_Global_Chrome_Upstream_Group@...iatek.com
Subject: Re: [v1 2/5] arm64: dts: mediatek: Correct UART clock of MT8192
Hi,
On Wed, Aug 25, 2021 at 09:11:17AM +0800, Chun-Jie Chen wrote:
> update uart0 and uart1 bus clock to the real one.
With the same commit message improvement from patch 1:
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@...labora.com>
Thanks,
Nícolas
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@...iatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 2b63d2ea6cb6..31d135e18784 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -327,7 +327,7 @@
> "mediatek,mt6577-uart";
> reg = <0 0x11002000 0 0x1000>;
> interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
> - clocks = <&clk26m>, <&clk26m>;
> + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
> clock-names = "baud", "bus";
> status = "disabled";
> };
> @@ -337,7 +337,7 @@
> "mediatek,mt6577-uart";
> reg = <0 0x11003000 0 0x1000>;
> interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
> - clocks = <&clk26m>, <&clk26m>;
> + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
> clock-names = "baud", "bus";
> status = "disabled";
> };
> --
> 2.18.0
>
>
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