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Message-ID: <20211210170113.30063-5-flora.fu@mediatek.com>
Date: Sat, 11 Dec 2021 01:01:09 +0800
From: Flora Fu <flora.fu@...iatek.com>
To: Matthias Brugger <matthias.bgg@...il.com>,
Liam Girdwood <lgirdwood@...il.com>,
Mark Brown <broonie@...nel.org>
CC: <linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-mediatek@...ts.infradead.org>,
Flora Fu <flora.fu@...iatek.com>,
"Yong Wu" <yong.wu@...iatek.com>, JB Tsai <jb.tsai@...iatek.com>,
Pi-Cheng Chen <pi-cheng.chen@...iatek.com>,
Chun-Jie Chen <chun-jie.chen@...iatek.com>
Subject: [PATCH v4 4/8] dt-bindings: soc: mediatek: apusys: Add new document for APU power domain
Document the bindings for APU power domain on MediaTek SoC.
Signed-off-by: Flora Fu <flora.fu@...iatek.com>
Reviewed-by: Rob Herring <robh@...nel.org>
---
.../soc/mediatek/mediatek,apu-pm.yaml | 144 ++++++++++++++++++
1 file changed, 144 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml
diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml
new file mode 100644
index 000000000000..e1b7d4030dc9
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml
@@ -0,0 +1,144 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2021 (C) MediaTek Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/mediatek/mediatek,apu-pm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek APU Power Domains
+
+maintainers:
+ - Flora Fu <flora.fu@...iatek.com>
+
+description: |
+ MediaTek AI Process Unit (APU) include support for power domains which can be
+ powered up/down by software.
+ APU subsys belonging to a power domain should contain a 'power-domains'
+ property that is a phandle for apuspm node representing the domain.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8192-apu-pm
+ - const: syscon
+
+ reg:
+ description: Address range of the APU power domain controller.
+ maxItems: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ '#power-domain-cells':
+ const: 1
+
+ vsram-supply:
+ description: apu sram regulator supply.
+
+ mediatek,scpsys:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: |
+ phandle to the device containing the scpsys register range.
+
+ mediatek,apu-conn:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: |
+ phandle to the device containing the scpsys apu conn register range.
+
+ mediatek,apu-conn1:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: |
+ phandle to the device containing the scpsys apu conn1 register range.
+
+ mediatek,apu-vcore:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: |
+ phandle to the device containing the scpsys apu vcore register range.
+
+patternProperties:
+ "^power-domain@[0-9a-f]+$":
+ type: object
+ description: |
+ Represents the power domains within the power controller node as
+ documented in Documentation/devicetree/bindings/power/power-domain.yaml.
+
+ properties:
+ reg:
+ description: Power domain index.
+ maxItems: 1
+
+ '#power-domain-cells':
+ description: |
+ Must be 0 for nodes representing a single PM domain and 1 for nodes
+ providing multiple PM.
+
+ clocks:
+ description: |
+ List of phandles of clocks list. Specify by order according to
+ power-up sequence.
+
+ clock-names:
+ description: |
+ List of names of clocks. Specify by order according to power-up
+ sequence.
+
+ assigned-clocks:
+ maxItems: 2
+
+ assigned-clock-parents:
+ maxItems: 2
+
+ domain-supply:
+ description: domain regulator supply.
+
+ required:
+ - reg
+ - '#power-domain-cells'
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - '#power-domain-cells'
+ - vsram-supply
+ - mediatek,scpsys
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8192-clk.h>
+ apuspm: power-domain@...f0000 {
+ compatible = "mediatek,mt8192-apu-pm", "syscon";
+ reg = <0x190f0000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+ vsram-supply = <&mt6359_vsram_md_ldo_reg>;
+ mediatek,scpsys = <&scpsys>;
+ mediatek,apu-conn = <&apu_conn>;
+ mediatek,apu-vcore = <&apu_vcore>;
+
+ apu_top: power-domain@0 {
+ reg = <0>;
+ #power-domain-cells = <0>;
+ clocks = <&topckgen CLK_TOP_DSP_SEL>,
+ <&topckgen CLK_TOP_IPU_IF_SEL>,
+ <&clk26m>,
+ <&topckgen CLK_TOP_UNIVPLL_D6_D2>;
+ clock-names = "clk_top_conn",
+ "clk_top_ipu_if",
+ "clk_off",
+ "clk_on_default";
+ assigned-clocks = <&topckgen CLK_TOP_DSP_SEL>,
+ <&topckgen CLK_TOP_IPU_IF_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+ <&topckgen CLK_TOP_UNIVPLL_D6_D2>;
+ domain-supply = <&mt6359_vproc1_buck_reg>;
+ };
+ };
--
2.18.0
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