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Message-ID: <CAGOxZ51nmoiiWdr3FYLBpg+WSyfnK3wsK+aDi_Q7NAxVVBQWHQ@mail.gmail.com>
Date: Sun, 19 Dec 2021 16:47:47 +0530
From: Alim Akhtar <alim.akhtar@...il.com>
To: Sam Protsenko <semen.protsenko@...aro.org>
Cc: Sylwester Nawrocki <s.nawrocki@...sung.com>,
Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>,
Chanwoo Choi <cw00.choi@...sung.com>,
Tomasz Figa <tomasz.figa@...il.com>,
Rob Herring <robh+dt@...nel.org>,
Stephen Boyd <sboyd@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
David Virag <virag.david003@...il.com>,
Paweł Chmiel <pawel.mikolaj.chmiel@...il.com>,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-clk@...r.kernel.org,
open list <linux-kernel@...r.kernel.org>,
linux-samsung-soc@...r.kernel.org
Subject: Re: [PATCH 1/2] dt-bindings: clock: exynos850: Add bindings for
Exynos850 sysreg clocks
On Mon, Nov 29, 2021 at 7:08 PM Sam Protsenko
<semen.protsenko@...aro.org> wrote:
>
> System Register is used to configure system behavior, like USI protocol,
> etc. SYSREG clocks should be provided to corresponding syscon nodes, to
> make it possible to modify SYSREG registers.
>
> While at it, add also missing PMU and GPIO clocks, which looks necessary
> and might be needed for corresponding Exynos850 features soon.
>
> Signed-off-by: Sam Protsenko <semen.protsenko@...aro.org>
> ---
> include/dt-bindings/clock/exynos850.h | 12 +++++++++---
> 1 file changed, 9 insertions(+), 3 deletions(-)
>
Looks good, feel free to add
Reviewed-by: Alim Akhtar <alim.akhtar@...sung.com>
> diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h
> index 8aa5e82af0d3..0b6a3c6a7c90 100644
> --- a/include/dt-bindings/clock/exynos850.h
> +++ b/include/dt-bindings/clock/exynos850.h
> @@ -82,7 +82,10 @@
> #define CLK_GOUT_I3C_PCLK 19
> #define CLK_GOUT_I3C_SCLK 20
> #define CLK_GOUT_SPEEDY_PCLK 21
> -#define APM_NR_CLK 22
> +#define CLK_GOUT_GPIO_ALIVE_PCLK 22
> +#define CLK_GOUT_PMU_ALIVE_PCLK 23
> +#define CLK_GOUT_SYSREG_APM_PCLK 24
> +#define APM_NR_CLK 25
>
> /* CMU_CMGP */
> #define CLK_RCO_CMGP 1
> @@ -99,7 +102,8 @@
> #define CLK_GOUT_CMGP_USI0_PCLK 12
> #define CLK_GOUT_CMGP_USI1_IPCLK 13
> #define CLK_GOUT_CMGP_USI1_PCLK 14
> -#define CMGP_NR_CLK 15
> +#define CLK_GOUT_SYSREG_CMGP_PCLK 15
> +#define CMGP_NR_CLK 16
>
> /* CMU_HSI */
> #define CLK_MOUT_HSI_BUS_USER 1
> @@ -167,7 +171,9 @@
> #define CLK_GOUT_MMC_EMBD_SDCLKIN 10
> #define CLK_GOUT_SSS_ACLK 11
> #define CLK_GOUT_SSS_PCLK 12
> -#define CORE_NR_CLK 13
> +#define CLK_GOUT_GPIO_CORE_PCLK 13
> +#define CLK_GOUT_SYSREG_CORE_PCLK 14
> +#define CORE_NR_CLK 15
>
> /* CMU_DPU */
> #define CLK_MOUT_DPU_USER 1
> --
> 2.30.2
>
--
Regards,
Alim
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