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Message-ID: <05d6a273-19f6-2147-75ba-1fff726a0f70@microchip.com>
Date: Thu, 23 Dec 2021 14:56:45 +0000
From: <Conor.Dooley@...rochip.com>
To: <krzysztof.kozlowski@...onical.com>, <linus.walleij@...aro.org>,
<bgolaszewski@...libre.com>, <robh+dt@...nel.org>,
<jassisinghbrar@...il.com>, <paul.walmsley@...ive.com>,
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<a.zummo@...ertech.it>, <alexandre.belloni@...tlin.com>,
<broonie@...nel.org>, <gregkh@...uxfoundation.org>,
<thierry.reding@...il.com>, <u.kleine-koenig@...gutronix.de>,
<lee.jones@...aro.org>, <linux-gpio@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
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CC: <geert@...ux-m68k.org>, <bin.meng@...driver.com>,
<heiko@...ech.de>, <Lewis.Hanly@...rochip.com>,
<Daire.McNamara@...rochip.com>, <Ivan.Griffin@...rochip.com>,
<atish.patra@....com>
Subject: Re: [PATCH v2 17/17] MAINTAINERS: update riscv/microchip entry
On 17/12/2021 15:09, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On 17/12/2021 10:33, conor.dooley@...rochip.com wrote:
>> From: Conor Dooley <conor.dooley@...rochip.com>
>>
>> Update the RISC-V/Microchip entry by adding the microchip dts
>> directory and myself as maintainer
>>
>> Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
>> ---
>> MAINTAINERS | 2 ++
>> 1 file changed, 2 insertions(+)
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 7a2345ce8521..3b1d6be7bd56 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -16348,8 +16348,10 @@ K: riscv
>>
>> RISC-V/MICROCHIP POLARFIRE SOC SUPPORT
>> M: Lewis Hanly <lewis.hanly@...rochip.com>
>> +M: Conor Dooley <conor.dooley@...rochip.com>
>> L: linux-riscv@...ts.infradead.org
>> S: Supported
>> +F: arch/riscv/boot/dts/microchip/
>> F: drivers/mailbox/mailbox-mpfs.c
>> F: drivers/soc/microchip/
>> F: include/soc/microchip/mpfs.h
>>
>
> Good to have the DTS covered, so FWIW:
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>
>
> You still should get Lewis' ack (unless he merges it)
Aye, it'll be an ack. We don't currently have a tree & would rather do
this via risc-v than the at91/sam arm soc tree.
>
> Best regards,
> Krzysztof
>
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