linux-kernel - Re: [PATCH v2 17/17] MAINTAINERS: update riscv/microchip entry

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Message-ID: <mhng-0e4cde83-cfa1-4bf6-9f2c-611d9a4ddb5f@palmer-ri-x1c9>
Date:   Thu, 23 Dec 2021 09:36:23 -0800 (PST)
From:   Palmer Dabbelt <palmer@...belt.com>
To:     Conor.Dooley@...rochip.com
CC:     krzysztof.kozlowski@...onical.com, linus.walleij@...aro.org,
        bgolaszewski@...libre.com, robh+dt@...nel.org,
        jassisinghbrar@...il.com, Paul Walmsley <paul.walmsley@...ive.com>,
        aou@...s.berkeley.edu, a.zummo@...ertech.it,
        alexandre.belloni@...tlin.com, broonie@...nel.org,
        Greg KH <gregkh@...uxfoundation.org>, thierry.reding@...il.com,
        u.kleine-koenig@...gutronix.de, lee.jones@...aro.org,
        linux-gpio@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-i2c@...r.kernel.org,
        linux-pwm@...r.kernel.org, linux-riscv@...ts.infradead.org,
        linux-crypto@...r.kernel.org, linux-rtc@...r.kernel.org,
        linux-spi@...r.kernel.org, linux-usb@...r.kernel.org,
        geert@...ux-m68k.org, bin.meng@...driver.com, heiko@...ech.de,
        Lewis.Hanly@...rochip.com, Daire.McNamara@...rochip.com,
        Ivan.Griffin@...rochip.com, Atish Patra <atishp@...osinc.com>
Subject:     Re: [PATCH v2 17/17] MAINTAINERS: update riscv/microchip entry

On Thu, 23 Dec 2021 06:56:45 PST (-0800), Conor.Dooley@...rochip.com wrote:
> On 17/12/2021 15:09, Krzysztof Kozlowski wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>> 
>> On 17/12/2021 10:33, conor.dooley@...rochip.com wrote:
>>> From: Conor Dooley <conor.dooley@...rochip.com>
>>>
>>> Update the RISC-V/Microchip entry by adding the microchip dts
>>> directory and myself as maintainer
>>>
>>> Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
>>> ---
>>>   MAINTAINERS | 2 ++
>>>   1 file changed, 2 insertions(+)
>>>
>>> diff --git a/MAINTAINERS b/MAINTAINERS
>>> index 7a2345ce8521..3b1d6be7bd56 100644
>>> --- a/MAINTAINERS
>>> +++ b/MAINTAINERS
>>> @@ -16348,8 +16348,10 @@ K:   riscv
>>>
>>>   RISC-V/MICROCHIP POLARFIRE SOC SUPPORT
>>>   M:   Lewis Hanly <lewis.hanly@...rochip.com>
>>> +M:   Conor Dooley <conor.dooley@...rochip.com>
>>>   L:   linux-riscv@...ts.infradead.org
>>>   S:   Supported
>>> +F:   arch/riscv/boot/dts/microchip/
>>>   F:   drivers/mailbox/mailbox-mpfs.c
>>>   F:   drivers/soc/microchip/
>>>   F:   include/soc/microchip/mpfs.h
>>>
>> 
>> Good to have the DTS covered, so FWIW:
>> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>
>> 
>> You still should get Lewis' ack (unless he merges it)
> Aye, it'll be an ack. We don't currently have a tree & would rather do 
> this via risc-v than the at91/sam arm soc tree.

WFM.  I'll be awaiting the ack.  I don't see any fundamental issues from 
my end, as long is it's got all the acks/reviews then I'm generally fine 
with this sort of stuff.  I'll take a look before merging it, I'm kind 
of buried right now.  Sorry!

>> 
>> Best regards,
>> Krzysztof
>> 
>