linux-kernel - Re: [PATCH] clk: renesas: r8a7799[05]: Add MLP clocks

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Message-ID: <e0a56147-e800-914b-1df3-51ca7003a69d@gmail.com>
Date:   Sun, 26 Dec 2021 20:46:50 +0300
From:   Sergei Shtylyov <sergei.shtylyov@...il.com>
To:     Nikita Yushchenko <nikita.yoush@...entembedded.com>,
        Geert Uytterhoeven <geert+renesas@...der.be>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>
Cc:     linux-renesas-soc@...r.kernel.org, linux-clk@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH] clk: renesas: r8a7799[05]: Add MLP clocks

On 25.12.2021 22:39, Nikita Yushchenko wrote:

> Add clocks for MLP modules on Renesas R-Car E3 and D3 SoCs.
> 
> Similar to other R-Car Gen3 SoC, exact information on parent for MLP
> clock on E3 and D3 is not available. However, since parent for this
> clocl is not anyhow software-controllable, the only harm from this

    s/clocl/clock/. :-)

> is inexact information exported via debugfs. So just keep the parent
> set in the same way as with other Gen3 SoCs.
> 
> Signed-off-by: Nikita Yushchenko <nikita.yoush@...entembedded.com>
[...]

MBR, Sergey