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Message-ID: <CAMuHMdW-S_SPgQmY6kxweNy4sYYKBorxnytk9c8101q7K2KB-w@mail.gmail.com>
Date: Mon, 10 Jan 2022 16:06:30 +0100
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Sergei Shtylyov <sergei.shtylyov@...il.com>
Cc: Nikita Yushchenko <nikita.yoush@...entembedded.com>,
Geert Uytterhoeven <geert+renesas@...der.be>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Linux-Renesas <linux-renesas-soc@...r.kernel.org>,
linux-clk <linux-clk@...r.kernel.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] clk: renesas: r8a7799[05]: Add MLP clocks
On Sun, Dec 26, 2021 at 6:46 PM Sergei Shtylyov
<sergei.shtylyov@...il.com> wrote:
> On 25.12.2021 22:39, Nikita Yushchenko wrote:
> > Add clocks for MLP modules on Renesas R-Car E3 and D3 SoCs.
> >
> > Similar to other R-Car Gen3 SoC, exact information on parent for MLP
> > clock on E3 and D3 is not available. However, since parent for this
> > clocl is not anyhow software-controllable, the only harm from this
>
> s/clocl/clock/. :-)
>
> > is inexact information exported via debugfs. So just keep the parent
> > set in the same way as with other Gen3 SoCs.
> >
> > Signed-off-by: Nikita Yushchenko <nikita.yoush@...entembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
i.e. will queue in renesas-clk-for-v5.18, with the typos fixed.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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