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Message-ID: <9c8d02ff-74a6-b8ba-c19b-9ee20da9af12@gmail.com>
Date: Wed, 29 Dec 2021 17:54:27 +0800
From: Like Xu <like.xu.linux@...il.com>
To: Stephane Eranian <eranian@...gle.com>, linux-kernel@...r.kernel.org
Cc: peterz@...radead.org, kim.phillips@....com, acme@...hat.com,
jolsa@...hat.com, songliubraving@...com, mpe@...erman.id.au,
maddy@...ux.ibm.com
Subject: Re: [PATCH v4 03/14] perf/x86/amd: add AMD Fam19h Branch Sampling
support
Hi Stephane,
On 11/12/2021 5:02 am, Stephane Eranian wrote:
> + * The BRS counter could be any counter, but there is no constraint on Fam19h,
> + * therefore all counters are equal and thus we pick the first one: PMC0
Are you assuming that no other counters can be enabled (guaranteed by the
patched perf context) when BRS is enabled ? Otherwise the hard-coding of
PMC0 may destroy scheduling freedom. Can we relax this condition?
Thanks,
Like Xu
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