linux-kernel - RE: [PATCH v3 16/22] kvm: x86: Add XCR0 support for Intel AMX

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Message-ID: <BN9PR11MB52767A662EE36412B166244B8C449@BN9PR11MB5276.namprd11.prod.outlook.com>
Date:   Wed, 29 Dec 2021 03:01:18 +0000
From:   "Tian, Kevin" <kevin.tian@...el.com>
To:     "Christopherson,, Sean" <seanjc@...gle.com>,
        "Liu, Jing2" <jing2.liu@...el.com>
CC:     "x86@...nel.org" <x86@...nel.org>,
        "kvm@...r.kernel.org" <kvm@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-doc@...r.kernel.org" <linux-doc@...r.kernel.org>,
        "linux-kselftest@...r.kernel.org" <linux-kselftest@...r.kernel.org>,
        "tglx@...utronix.de" <tglx@...utronix.de>,
        "mingo@...hat.com" <mingo@...hat.com>,
        "bp@...en8.de" <bp@...en8.de>,
        "dave.hansen@...ux.intel.com" <dave.hansen@...ux.intel.com>,
        "pbonzini@...hat.com" <pbonzini@...hat.com>,
        "corbet@....net" <corbet@....net>,
        "shuah@...nel.org" <shuah@...nel.org>,
        "Nakajima, Jun" <jun.nakajima@...el.com>,
        "jing2.liu@...ux.intel.com" <jing2.liu@...ux.intel.com>,
        "Zeng, Guang" <guang.zeng@...el.com>,
        "Wang, Wei W" <wei.w.wang@...el.com>,
        "Zhong, Yang" <yang.zhong@...el.com>
Subject: RE: [PATCH v3 16/22] kvm: x86: Add XCR0 support for Intel AMX

> From: Sean Christopherson <seanjc@...gle.com>
> Sent: Wednesday, December 29, 2021 8:21 AM
> 
> On Wed, Dec 22, 2021, Jing Liu wrote:
> > Two XCR0 bits are defined for AMX to support XSAVE mechanism. Bit 17
> > is for tilecfg and bit 18 is for tiledata.
> >
> > The value of XCR0[17:18] is always either 00b or 11b.
> 
> Is that an SDM requirement, or an arbitrary Linux/KVM requirement?

SDM requirement

> 
> > Also, SDM
> > recommends that only 64-bit operating systems enable Intel AMX by
> > setting XCR0[18:17]. If a 32-bit guest tries to set dynamic bits, it
> 
> This is wrong.  It has nothing to do with 32-bit guests.  The restriction is on
> 32-bit _host kernels_, which I'm guessing never set the tile bits in _host_
> XCR0.

make sense.

> 
> > fails to pass vcpu->arch.guest_supported_xcr0 check and gets a #GP.
> >
> > Signed-off-by: Yang Zhong <yang.zhong@...el.com>
> > Signed-off-by: Jing Liu <jing2.liu@...el.com>
> > ---
> >  arch/x86/kvm/x86.c | 8 +++++++-
> >  1 file changed, 7 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
> > index a48a89f73027..c558c098979a 100644
> > --- a/arch/x86/kvm/x86.c
> > +++ b/arch/x86/kvm/x86.c
> > @@ -210,7 +210,7 @@ static struct kvm_user_return_msrs __percpu
> *user_return_msrs;
> >  #define KVM_SUPPORTED_XCR0     (XFEATURE_MASK_FP |
> XFEATURE_MASK_SSE \
> >  				| XFEATURE_MASK_YMM |
> XFEATURE_MASK_BNDREGS \
> >  				| XFEATURE_MASK_BNDCSR |
> XFEATURE_MASK_AVX512 \
> > -				| XFEATURE_MASK_PKRU)
> > +				| XFEATURE_MASK_PKRU |
> XFEATURE_MASK_XTILE)
> >
> >  u64 __read_mostly host_efer;
> >  EXPORT_SYMBOL_GPL(host_efer);
> > @@ -990,6 +990,12 @@ static int __kvm_set_xcr(struct kvm_vcpu *vcpu,
> u32 index, u64 xcr)
> >  		if ((xcr0 & XFEATURE_MASK_AVX512) !=
> XFEATURE_MASK_AVX512)
> >  			return 1;
> >  	}
> > +
> > +#ifdef CONFIG_X86_64
> 
> Drop the #ifdef, it adds no meaningful value and requires the reader to think
> far harder than they should have.  Yes, it's technically dead code for 32-bit
> KVM,
> but no one cares about performance of 32-bit KVM, and in any case it's
> extremely
> unlikely this will be anything but noise.

ok

> 
> > +	if ((xcr0 & XFEATURE_MASK_XTILE) &&
> > +	    ((xcr0 & XFEATURE_MASK_XTILE) != XFEATURE_MASK_XTILE))
> > +		return 1;
> > +#endif
> >  	vcpu->arch.xcr0 = xcr0;
> >
> >  	if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
> > --
> > 2.27.0
> >