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Message-Id: <1640856276-14697-1-git-send-email-quic_rajeevny@quicinc.com>
Date: Thu, 30 Dec 2021 14:54:34 +0530
From: Rajeev Nandan <quic_rajeevny@...cinc.com>
To: dri-devel@...ts.freedesktop.org, linux-arm-msm@...r.kernel.org,
freedreno@...ts.freedesktop.org, devicetree@...r.kernel.org
Cc: Rajeev Nandan <quic_rajeevny@...cinc.com>,
linux-kernel@...r.kernel.org, sean@...rly.run, robdclark@...il.com,
robh+dt@...nel.org, robh@...nel.org, quic_abhinavk@...cinc.com,
quic_kalyant@...cinc.com, quic_mkrishn@...cinc.com,
jonathan@...ek.ca, dmitry.baryshkov@...aro.org, airlied@...ux.ie,
daniel@...ll.ch, swboyd@...omium.org
Subject: [v1 0/2] drm/msm/dsi: Add 10nm dsi phy tuning configuration support
This series is to add DSI PHY tuning support in Qualcomm Snapdragon
SoCs with 10nm DSI PHY e.g. SC7180
In most cases the default values of DSI PHY tuning registers
should be sufficient as they are fully optimized. However, in
some cases (for example, where extreme board parasitics cause
the eye shape to degrade), the override bits can be used to
improve the signal quality.
As per the MSM DSI PHY (10nm) tuning guideline, the drive strength
can be adjusted using DSIPHY_RESCODE_OFFSET_TOP & DSIPHY_RESCODE_OFFSET_BOT
registers, and the drive level can be adjusted using DSIPHY_CMN_VREG_CTRL
register.
Add DSI PHY tuning support for 10nm PHY. This can be extended to other
DSI PHY versions if needed. Number of registers to configure the PHY
tuning per lane can be different for different versions of the DSI PHY.
I tried to make it generic so that it can be extended to other versions.
Rajeev Nandan (2):
dt-bindings: msm/dsi: Add 10nm dsi phy tuning properties
drm/msm/dsi: Add 10nm dsi phy tuning configuration support
.../bindings/display/msm/dsi-phy-10nm.yaml | 19 ++++++++
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 55 ++++++++++++++++++++++
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 23 +++++++++
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 31 +++++++++---
4 files changed, 122 insertions(+), 6 deletions(-)
--
2.7.4
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