linux-kernel - [v1 1/2] dt-bindings: msm/dsi: Add 10nm dsi phy tuning properties

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Message-Id: <1640856276-14697-2-git-send-email-quic_rajeevny@quicinc.com>
Date:   Thu, 30 Dec 2021 14:54:35 +0530
From:   Rajeev Nandan <quic_rajeevny@...cinc.com>
To:     dri-devel@...ts.freedesktop.org, linux-arm-msm@...r.kernel.org,
        freedreno@...ts.freedesktop.org, devicetree@...r.kernel.org
Cc:     Rajeev Nandan <quic_rajeevny@...cinc.com>,
        linux-kernel@...r.kernel.org, sean@...rly.run, robdclark@...il.com,
        robh+dt@...nel.org, robh@...nel.org, quic_abhinavk@...cinc.com,
        quic_kalyant@...cinc.com, quic_mkrishn@...cinc.com,
        jonathan@...ek.ca, dmitry.baryshkov@...aro.org, airlied@...ux.ie,
        daniel@...ll.ch, swboyd@...omium.org
Subject: [v1 1/2] dt-bindings: msm/dsi: Add 10nm dsi phy tuning properties

Add 10nm dsi phy tuning properties for phy drive strength and
phy drive level adjustemnt.

Signed-off-by: Rajeev Nandan <quic_rajeevny@...cinc.com>
---
 .../devicetree/bindings/display/msm/dsi-phy-10nm.yaml | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml
index 4399715..9406982 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml
@@ -35,6 +35,18 @@ properties:
       Connected to DSI0_MIPI_DSI_PLL_VDDA0P9 pin for sc7180 target and
       connected to VDDA_MIPI_DSI_0_PLL_0P9 pin for sdm845 target
 
+  phy-drive-strength-cfg:
+    type: array
+    description:
+      Register values of DSIPHY_RESCODE_OFFSET_TOP and DSIPHY_RESCODE_OFFSET_BOT
+      for all five lanes to adjust the phy drive strength.
+
+  phy-drive-level-cfg:
+    type: array
+    description:
+      Register values of DSIPHY_RESCODE_OFFSET_TOP for all five lanes to adjust
+      phy drive level/amplitude.
+
 required:
   - compatible
   - reg
@@ -64,5 +76,12 @@ examples:
          clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
                   <&rpmhcc RPMH_CXO_CLK>;
          clock-names = "iface", "ref";
+
+         phy-drive-strength-cfg = [00 00
+                                   00 00
+                                   00 00
+                                   00 00
+                                   00 00];
+         phy-drive-level-cfg = [59 59 59 59 59];
      };
 ...
-- 
2.7.4