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Message-ID: <Yc3kbiZWeLBcCrw9@zn.tnic>
Date: Thu, 30 Dec 2021 17:55:10 +0100
From: Borislav Petkov <bp@...e.de>
To: Huang Rui <ray.huang@....com>
Cc: "Rafael J . Wysocki" <rafael.j.wysocki@...el.com>,
Viresh Kumar <viresh.kumar@...aro.org>,
Shuah Khan <skhan@...uxfoundation.org>,
Peter Zijlstra <peterz@...radead.org>,
Ingo Molnar <mingo@...nel.org>,
Giovanni Gherdovich <ggherdovich@...e.cz>,
Steven Rostedt <rostedt@...dmis.org>, linux-pm@...r.kernel.org,
Deepak Sharma <deepak.sharma@....com>,
Alex Deucher <alexander.deucher@....com>,
Mario Limonciello <mario.limonciello@....com>,
Steven Noonan <steven@...vesoftware.com>,
Nathan Fontenot <nathan.fontenot@....com>,
Jinzhou Su <Jinzhou.Su@....com>,
Xiaojian Du <Xiaojian.Du@....com>,
linux-kernel@...r.kernel.org, x86@...nel.org
Subject: Re: [PATCH v7 02/14] x86/msr: Add AMD CPPC MSR definitions
On Fri, Dec 24, 2021 at 09:04:56AM +0800, Huang Rui wrote:
> AMD CPPC (Collaborative Processor Performance Control) function uses MSR
> registers to manage the performance hints. So add the MSR register macro
> here.
>
> Signed-off-by: Huang Rui <ray.huang@....com>
> ---
> arch/x86/include/asm/msr-index.h | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
Acked-by: Borislav Petkov <bp@...e.de>
--
Regards/Gruss,
Boris.
SUSE Software Solutions Germany GmbH, GF: Ivo Totev, HRB 36809, AG Nürnberg
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