| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <48493504-8877-b78d-0476-118a8b1441e0@collabora.com>
Date: Tue, 4 Jan 2022 16:53:22 +0100
From: AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>
To: Yong Wu <yong.wu@...iatek.com>, Joerg Roedel <joro@...tes.org>,
Rob Herring <robh+dt@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>,
Will Deacon <will@...nel.org>,
Robin Murphy <robin.murphy@....com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>,
Tomasz Figa <tfiga@...omium.org>,
linux-mediatek@...ts.infradead.org, srv_heupstream@...iatek.com,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
iommu@...ts.linux-foundation.org,
Hsin-Yi Wang <hsinyi@...omium.org>, youlin.pei@...iatek.com,
anan.sun@...iatek.com, chao.hao@...iatek.com,
yen-chang.chen@...iatek.com
Subject: Re: [PATCH v3 28/33] iommu/mediatek: Add bank_nr and bank_enable
Il 23/09/21 13:58, Yong Wu ha scritto:
> Prepare for supporting multi banks, Adds two variables in the plat_data:
> bank_nr: the bank number that this SoC support;
> bank_enable: list if the banks is enabled.
>
> Add them for all the current SoC, bank_nr always is 1 and only
> bank_enable[0] is enabled.
>
> Signed-off-by: Yong Wu <yong.wu@...iatek.com>
> ---
> drivers/iommu/mtk_iommu.c | 18 ++++++++++++++++++
> drivers/iommu/mtk_iommu.h | 3 +++
> 2 files changed, 21 insertions(+)
>
> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> index c139675d99e6..4ad85469f68f 100644
> --- a/drivers/iommu/mtk_iommu.c
> +++ b/drivers/iommu/mtk_iommu.c
> @@ -1134,6 +1134,8 @@ static const struct mtk_iommu_plat_data mt2712_data = {
> NOT_STD_AXI_MODE | MTK_IOMMU_TYPE_MM,
> .hw_list = &m4ulist,
> .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
> + .bank_nr = 1,
> + .bank_enable = {true},
> .iova_region = single_domain,
> .iova_region_nr = ARRAY_SIZE(single_domain),
> .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}},
> @@ -1144,6 +1146,8 @@ static const struct mtk_iommu_plat_data mt6779_data = {
> .flags = HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | WR_THROT_EN |
> NOT_STD_AXI_MODE | MTK_IOMMU_TYPE_MM,
> .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
> + .bank_nr = 1,
> + .bank_enable = {true},
> .iova_region = single_domain,
> .iova_region_nr = ARRAY_SIZE(single_domain),
> .larbid_remap = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}},
> @@ -1154,6 +1158,8 @@ static const struct mtk_iommu_plat_data mt8167_data = {
> .flags = RESET_AXI | HAS_LEGACY_IVRP_PADDR | NOT_STD_AXI_MODE |
> MTK_IOMMU_TYPE_MM,
> .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
> + .bank_nr = 1,
> + .bank_enable = {true},
> .iova_region = single_domain,
> .iova_region_nr = ARRAY_SIZE(single_domain),
> .larbid_remap = {{0}, {1}, {2}}, /* Linear mapping. */
> @@ -1165,6 +1171,8 @@ static const struct mtk_iommu_plat_data mt8173_data = {
> HAS_LEGACY_IVRP_PADDR | NOT_STD_AXI_MODE |
> MTK_IOMMU_TYPE_MM,
> .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
> + .bank_nr = 1,
> + .bank_enable = {true},
> .iova_region = single_domain,
> .iova_region_nr = ARRAY_SIZE(single_domain),
> .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */
> @@ -1174,6 +1182,8 @@ static const struct mtk_iommu_plat_data mt8183_data = {
> .m4u_plat = M4U_MT8183,
> .flags = RESET_AXI | MTK_IOMMU_TYPE_MM,
> .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
> + .bank_nr = 1,
> + .bank_enable = {true},
> .iova_region = single_domain,
> .iova_region_nr = ARRAY_SIZE(single_domain),
> .larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}},
> @@ -1185,6 +1195,8 @@ static const struct mtk_iommu_plat_data mt8192_data = {
> WR_THROT_EN | IOVA_34_EN | NOT_STD_AXI_MODE |
> MTK_IOMMU_TYPE_MM,
> .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
> + .bank_nr = 1,
> + .bank_enable = {true},
> .iova_region = mt8192_multi_dom,
> .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
> .larbid_remap = {{0}, {1}, {4, 5}, {7}, {2}, {9, 11, 19, 20},
> @@ -1196,6 +1208,8 @@ static const struct mtk_iommu_plat_data mt8195_data_infra = {
> .flags = WR_THROT_EN | DCM_DISABLE |
> MTK_IOMMU_TYPE_INFRA | IFA_IOMMU_PCIe_SUPPORT,
> .pericfg_comp_str = "mediatek,mt8195-pericfg_ao",
> + .bank_nr = 1,
> + .bank_enable = {true},
> .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
> .iova_region = single_domain,
> .iova_region_nr = ARRAY_SIZE(single_domain),
> @@ -1208,6 +1222,8 @@ static const struct mtk_iommu_plat_data mt8195_data_vdo = {
> SHARE_PGTABLE | MTK_IOMMU_TYPE_MM,
> .hw_list = &m4ulist,
> .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
> + .bank_nr = 1,
> + .bank_enable = {true},
> .iova_region = mt8192_multi_dom,
> .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
> .larbid_remap = {{2, 0}, {21}, {24}, {7}, {19}, {9, 10, 11},
> @@ -1221,6 +1237,8 @@ static const struct mtk_iommu_plat_data mt8195_data_vpp = {
> SHARE_PGTABLE | MTK_IOMMU_TYPE_MM,
> .hw_list = &m4ulist,
> .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
> + .bank_nr = 1,
> + .bank_enable = {true},
> .iova_region = mt8192_multi_dom,
> .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
> .larbid_remap = {{1}, {3}, {22, 0, 0, 0, 23}, {8},
> diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
> index 881fade8d39a..dc0190edebf0 100644
> --- a/drivers/iommu/mtk_iommu.h
> +++ b/drivers/iommu/mtk_iommu.h
> @@ -62,6 +62,9 @@ struct mtk_iommu_plat_data {
> struct list_head *hw_list;
> unsigned int iova_region_nr;
> const struct mtk_iommu_iova_region *iova_region;
> +
> + unsigned int bank_nr;
As said in the review for patch 26/33, maybe this can be renamed as `num_banks`
instead... and also, this can be a `u8` to save some memory.
> + bool bank_enable[MTK_IOMMU_BANK_MAX];
> unsigned char larbid_remap[MTK_LARB_COM_MAX][MTK_LARB_SUBCOM_MAX];
> };
>
>
Powered by blists - more mailing lists