lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
Open Source and information security mailing list archives
| ||
|
Date: Wed, 12 Jan 2022 00:53:12 +0000 From: Joel Stanley <joel@....id.au> To: Bartosz Golaszewski <brgl@...ev.pl> Cc: Steven Lee <steven_lee@...eedtech.com>, Andrew Jeffery <andrew@...id.au>, Linus Walleij <linus.walleij@...aro.org>, "open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>, "moderated list:ARM/ASPEED MACHINE SUPPORT" <linux-arm-kernel@...ts.infradead.org>, "moderated list:ARM/ASPEED MACHINE SUPPORT" <linux-aspeed@...ts.ozlabs.org>, open list <linux-kernel@...r.kernel.org>, Hongwei Zhang <Hongweiz@....com>, Ryan Chen <ryan_chen@...eedtech.com>, Billy Tsai <billy_tsai@...eedtech.com> Subject: Re: [PATCH v1 1/1] gpio: gpio-aspeed-sgpio: Fix wrong hwirq base in irq handler On Mon, 3 Jan 2022 at 09:50, Bartosz Golaszewski <brgl@...ev.pl> wrote: > > On Wed, Dec 22, 2021 at 10:18 AM Bartosz Golaszewski <brgl@...ev.pl> wrote: > > > > On Tue, Dec 14, 2021 at 5:03 AM Steven Lee <steven_lee@...eedtech.com> wrote: > > > > > > Each aspeed sgpio bank has 64 gpio pins(32 input pins and 32 output pins). > > > The hwirq base for each sgpio bank should be multiples of 64 rather than > > > multiples of 32. > > > > > > Signed-off-by: Steven Lee <steven_lee@...eedtech.com> > > > --- > > > drivers/gpio/gpio-aspeed-sgpio.c | 2 +- > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c > > > index 3d6ef37a7702..b3a9b8488f11 100644 > > > --- a/drivers/gpio/gpio-aspeed-sgpio.c > > > +++ b/drivers/gpio/gpio-aspeed-sgpio.c > > > @@ -395,7 +395,7 @@ static void aspeed_sgpio_irq_handler(struct irq_desc *desc) > > > reg = ioread32(bank_reg(data, bank, reg_irq_status)); > > > > > > for_each_set_bit(p, ®, 32) > > > - generic_handle_domain_irq(gc->irq.domain, i * 32 + p * 2); > > > + generic_handle_domain_irq(gc->irq.domain, (i * 32 + p) * 2); > > > } > > > > > > chained_irq_exit(ic, desc); > > > -- > > > 2.17.1 > > > > > > > Joel, Andrew: any comments on this? I'd like to send it upstream tomorrow. > > > > Bart > > I don't want to delay it anymore, it looks good so I queued it for fixes. Thanks for queuing. We were on leave over the holiday break, so no time for reviewing kernel patches. Cheers, Joel
Powered by blists - more mailing lists