[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <Yd708EjQNEa9dFXZ@hirez.programming.kicks-ass.net>
Date: Wed, 12 Jan 2022 16:34:08 +0100
From: Peter Zijlstra <peterz@...radead.org>
To: David Laight <David.Laight@...lab.com>
Cc: 'Mathieu Desnoyers' <mathieu.desnoyers@...icios.com>,
Christian Brauner <christian.brauner@...ntu.com>,
Christian Brauner <brauner@...nel.org>,
linux-kernel <linux-kernel@...r.kernel.org>,
Thomas Gleixner <tglx@...utronix.de>,
paulmck <paulmck@...nel.org>, Boqun Feng <boqun.feng@...il.com>,
"H. Peter Anvin" <hpa@...or.com>, Paul Turner <pjt@...gle.com>,
linux-api <linux-api@...r.kernel.org>,
Florian Weimer <fw@...eb.enyo.de>, carlos <carlos@...hat.com>
Subject: Re: [RFC PATCH v2 1/2] rseq: x86: implement abort-at-ip extension
On Wed, Jan 12, 2022 at 03:15:27PM +0000, David Laight wrote:
> From: Mathieu Desnoyers
> > Sent: 12 January 2022 15:06
> >
> > ----- On Jan 12, 2022, at 9:58 AM, David Laight David.Laight@...LAB.COM wrote:
> >
> > >> * [*] The openrisc, powerpc64 and x86-64 architectures define a "redzone" as a
> > >> * stack area beyond the stack pointer which can be used by the compiler
> > >> * to store local variables in leaf functions.
> > >
> > > I wonder if that is really worth the trouble it causes!
> > > By the time a function is spilling values to stack the cost
> > > of a %sp update is almost certainly noise.
> > >
> > > Someone clearly thought it was a 'good idea (tm)'.
> >
> > I must admit that I've been surprised to learn about these redzones. Thanks for
> > pointing them out to me, it was clearly a blind spot. I suspect it would be useful
> > to introduce per-architecture KERNEL_REDZONE, USER_REDZONE and COMPAT_USER_REDZONE
> > with a asm-generic version defining them to 0, with proper documentation. It would
> > make it clearer to kernel developers working on stuff similar to signal handler
> > delivery that they need to consider these carefully.
>
> They can never be used in kernel - any ISR would overwrite them.
That depends on how the architecture does exceptions; also consider:
https://www.intel.com/content/www/us/en/develop/download/flexible-return-and-event-delivery-specification.html
Powered by blists - more mailing lists