linux-kernel - Re: [PATCH] x86/cpufeatures: Move the definition of X86_FEATURE_AMX

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Wed, 19 Jan 2022 11:41:31 +0800
From:   Like Xu <like.xu.linux@...il.com>
To:     Dave Hansen <dave.hansen@...el.com>
Cc:     Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
        "H . Peter Anvin" <hpa@...or.com>, x86@...nel.org,
        Jing Liu <jing2.liu@...el.com>, linux-kernel@...r.kernel.org,
        "Bae, Chang Seok" <chang.seok.bae@...el.com>,
        Paolo Bonzini <pbonzini@...hat.com>,
        Thomas Gleixner <tglx@...utronix.de>
Subject: Re: [PATCH] x86/cpufeatures: Move the definition of X86_FEATURE_AMX_*
 to the word 18

On 19/1/2022 1:15 am, Paolo Bonzini wrote:
> On 1/18/22 18:11, Dave Hansen wrote:
>> What tree is this against?  I see BF16 and INT8 in some old versions of
>> Chang's patches, but not current kernels.  All I see right now in
>> tip/master is:
>>
>>> #define X86_FEATURE_AMX_TILE            (18*32+24) /* AMX tile ...
>>
>> It's still in the wrong spot, but the other two features aren't there.
> 
> It was added for the KVM side of AMX (commit 690a757d610e, "kvm: x86: Add CPUID 
> support for Intel AMX") and is in Linus's tree.
> 
> Paolo
> 
> 
>>> We have defined the word 18 for Intel-defined CPU features from CPUID level> 
>>> 0x00000007:0 (EDX). Let's move the definitions of X86_FEATURE_AMX_* to
>> the> right entry to prevent misinterpretation. No functional change
>> intended.
>> Please, no "we's" in changelogs.  Don't say, "let's move".  Just say:
>> "Move..." >>
>> The subject could probably also be trimmed a bit.  Perhaps:
>>
>>     x86/cpu: Move AMX CPU feature defines to correct word location
>>
>>
> 

Thanks Dave and Paolo.  Just for your convenience:

 From 588c2221999c1f5860188a7cbaeb0d4f80c6d727 Mon Sep 17 00:00:00 2001
From: Like Xu <likexu@...cent.com>
Date: Mon, 17 Jan 2022 14:23:44 +0800
Subject: [PATCH v2] x86/cpufeatures: Move AMX CPU feature defines to correct
  word location

From: Like Xu <likexu@...cent.com>

The word 18 for Intel-defined CPU features from CPUID level 0x00000007:0 (EDX)
has been defined in the same file. Move the definitions of X86_FEATURE_AMX_* to
the right entry to prevent misinterpretation. No functional change intended.

Signed-off-by: Like Xu <likexu@...cent.com>
Reviewed-by: Paolo Bonzini <pbonzini@...hat.com>
---
v1 -> v2 Changelog:
- Refine the commit message and subject; (Dave)

  arch/x86/include/asm/cpufeatures.h | 6 +++---
  1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 6db4e2932b3d..5cd22090e53d 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -299,9 +299,6 @@
  /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
  #define X86_FEATURE_AVX_VNNI		(12*32+ 4) /* AVX VNNI instructions */
  #define X86_FEATURE_AVX512_BF16		(12*32+ 5) /* AVX512 BFLOAT16 instructions */
-#define X86_FEATURE_AMX_BF16		(18*32+22) /* AMX bf16 Support */
-#define X86_FEATURE_AMX_TILE		(18*32+24) /* AMX tile Support */
-#define X86_FEATURE_AMX_INT8		(18*32+25) /* AMX int8 Support */

  /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
  #define X86_FEATURE_CLZERO		(13*32+ 0) /* CLZERO instruction */
@@ -390,7 +387,10 @@
  #define X86_FEATURE_TSXLDTRK		(18*32+16) /* TSX Suspend Load Address Tracking */
  #define X86_FEATURE_PCONFIG		(18*32+18) /* Intel PCONFIG */
  #define X86_FEATURE_ARCH_LBR		(18*32+19) /* Intel ARCH LBR */
+#define X86_FEATURE_AMX_BF16		(18*32+22) /* AMX bf16 Support */
  #define X86_FEATURE_AVX512_FP16		(18*32+23) /* AVX512 FP16 */
+#define X86_FEATURE_AMX_TILE		(18*32+24) /* AMX tile Support */
+#define X86_FEATURE_AMX_INT8		(18*32+25) /* AMX int8 Support */
  #define X86_FEATURE_SPEC_CTRL		(18*32+26) /* "" Speculation Control (IBRS + 
IBPB) */
  #define X86_FEATURE_INTEL_STIBP		(18*32+27) /* "" Single Thread Indirect 
Branch Predictors */
  #define X86_FEATURE_FLUSH_L1D		(18*32+28) /* Flush L1D cache */
-- 
2.33.1