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Message-ID: <20220123033306.29799-1-qizhong.cheng@mediatek.com>
Date: Sun, 23 Jan 2022 11:33:06 +0800
From: qizhong cheng <qizhong.cheng@...iatek.com>
To: Ryder Lee <ryder.lee@...iatek.com>,
Jianjun Wang <jianjun.wang@...iatek.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
Krzysztof WilczyĆski <kw@...ux.com>,
Bjorn Helgaas <bhelgaas@...gle.com>
CC: <linux-pci@...r.kernel.org>, <linux-mediatek@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<qizhong.cheng@...iatek.com>, <chuanjia.liu@...iatek.com>
Subject: [PATCH] PCI: mediatek: Change MSI interrupt processing sequence
As an edge-triggered interrupts, its interrupt status should be cleared
before dispatch to the handler of device.
Signed-off-by: qizhong cheng <qizhong.cheng@...iatek.com>
---
drivers/pci/controller/pcie-mediatek.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
index 2f3f974977a3..705ea33758b1 100644
--- a/drivers/pci/controller/pcie-mediatek.c
+++ b/drivers/pci/controller/pcie-mediatek.c
@@ -624,12 +624,12 @@ static void mtk_pcie_intr_handler(struct irq_desc *desc)
if (status & MSI_STATUS){
unsigned long imsi_status;
+ /* Clear MSI interrupt status */
+ writel(MSI_STATUS, port->base + PCIE_INT_STATUS);
while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) {
for_each_set_bit(bit, &imsi_status, MTK_MSI_IRQS_NUM)
generic_handle_domain_irq(port->inner_domain, bit);
}
- /* Clear MSI interrupt status */
- writel(MSI_STATUS, port->base + PCIE_INT_STATUS);
}
}
--
2.25.1
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