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Message-ID: <CAGXv+5EcAXFTnjkbeU4f3J2s4Ue5zxrN4QgS=t54BnLX8Gkw2w@mail.gmail.com>
Date: Mon, 24 Jan 2022 11:12:49 +0800
From: Chen-Yu Tsai <wenst@...omium.org>
To: qizhong cheng <qizhong.cheng@...iatek.com>
Cc: Ryder Lee <ryder.lee@...iatek.com>,
Jianjun Wang <jianjun.wang@...iatek.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
Krzysztof WilczyĆski <kw@...ux.com>,
Bjorn Helgaas <bhelgaas@...gle.com>, linux-pci@...r.kernel.org,
linux-mediatek@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, chuanjia.liu@...iatek.com
Subject: Re: [PATCH] PCI: mediatek: Change MSI interrupt processing sequence
Hi,
On Sun, Jan 23, 2022 at 11:34 AM qizhong cheng
<qizhong.cheng@...iatek.com> wrote:
>
> As an edge-triggered interrupts, its interrupt status should be cleared
> before dispatch to the handler of device.
I'm curious, is this just a code correction or are there real world
cases where something fails?
Also, please add a Fixes tag and maybe Cc stable so this gets backported
automatically.
ChenYu
> Signed-off-by: qizhong cheng <qizhong.cheng@...iatek.com>
> ---
> drivers/pci/controller/pcie-mediatek.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
> index 2f3f974977a3..705ea33758b1 100644
> --- a/drivers/pci/controller/pcie-mediatek.c
> +++ b/drivers/pci/controller/pcie-mediatek.c
> @@ -624,12 +624,12 @@ static void mtk_pcie_intr_handler(struct irq_desc *desc)
> if (status & MSI_STATUS){
> unsigned long imsi_status;
>
> + /* Clear MSI interrupt status */
> + writel(MSI_STATUS, port->base + PCIE_INT_STATUS);
> while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) {
> for_each_set_bit(bit, &imsi_status, MTK_MSI_IRQS_NUM)
> generic_handle_domain_irq(port->inner_domain, bit);
> }
> - /* Clear MSI interrupt status */
> - writel(MSI_STATUS, port->base + PCIE_INT_STATUS);
> }
> }
>
> --
> 2.25.1
>
>
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> Linux-mediatek@...ts.infradead.org
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