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Message-ID: <CAL_JsqLBwHK+M_Tk4YxAHxaSgUm7sFvov7-UC3TdDhhPWtaqew@mail.gmail.com>
Date: Mon, 24 Jan 2022 08:53:24 -0600
From: Rob Herring <robh@...nel.org>
To: Andy Gross <agross@...nel.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH] arm64: dts: qcom: Fix msm8998 cache nodes
On Fri, Dec 17, 2021 at 3:11 PM Rob Herring <robh@...nel.org> wrote:
>
> The msm8998 cache nodes have some issues. First, L1 caches are described
> within cpu nodes, not as separate nodes. The 'next-level-cache' property
> is of course in the correct location, otherwise the cache hierarchy
> walking would not work. Remove all the L1 cache nodes.
>
> Second, 'arm,arch-cache' is not a documented compatible string. "cache"
> is a sufficient compatible string for the Arm architected caches.
>
> Signed-off-by: Rob Herring <robh@...nel.org>
> ---
> arch/arm64/boot/dts/qcom/msm8998.dtsi | 52 ++-------------------------
> 1 file changed, 2 insertions(+), 50 deletions(-)
Ping
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
> index 408f265e277b..00adee461b52 100644
> --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
> @@ -138,15 +138,9 @@ CPU0: cpu@0 {
> cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
> next-level-cache = <&L2_0>;
> L2_0: l2-cache {
> - compatible = "arm,arch-cache";
> + compatible = "cache";
> cache-level = <2>;
> };
> - L1_I_0: l1-icache {
> - compatible = "arm,arch-cache";
> - };
> - L1_D_0: l1-dcache {
> - compatible = "arm,arch-cache";
> - };
> };
>
> CPU1: cpu@1 {
> @@ -157,12 +151,6 @@ CPU1: cpu@1 {
> capacity-dmips-mhz = <1024>;
> cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
> next-level-cache = <&L2_0>;
> - L1_I_1: l1-icache {
> - compatible = "arm,arch-cache";
> - };
> - L1_D_1: l1-dcache {
> - compatible = "arm,arch-cache";
> - };
> };
>
> CPU2: cpu@2 {
> @@ -173,12 +161,6 @@ CPU2: cpu@2 {
> capacity-dmips-mhz = <1024>;
> cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
> next-level-cache = <&L2_0>;
> - L1_I_2: l1-icache {
> - compatible = "arm,arch-cache";
> - };
> - L1_D_2: l1-dcache {
> - compatible = "arm,arch-cache";
> - };
> };
>
> CPU3: cpu@3 {
> @@ -189,12 +171,6 @@ CPU3: cpu@3 {
> capacity-dmips-mhz = <1024>;
> cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
> next-level-cache = <&L2_0>;
> - L1_I_3: l1-icache {
> - compatible = "arm,arch-cache";
> - };
> - L1_D_3: l1-dcache {
> - compatible = "arm,arch-cache";
> - };
> };
>
> CPU4: cpu@100 {
> @@ -206,15 +182,9 @@ CPU4: cpu@100 {
> cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
> next-level-cache = <&L2_1>;
> L2_1: l2-cache {
> - compatible = "arm,arch-cache";
> + compatible = "cache";
> cache-level = <2>;
> };
> - L1_I_100: l1-icache {
> - compatible = "arm,arch-cache";
> - };
> - L1_D_100: l1-dcache {
> - compatible = "arm,arch-cache";
> - };
> };
>
> CPU5: cpu@101 {
> @@ -225,12 +195,6 @@ CPU5: cpu@101 {
> capacity-dmips-mhz = <1536>;
> cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
> next-level-cache = <&L2_1>;
> - L1_I_101: l1-icache {
> - compatible = "arm,arch-cache";
> - };
> - L1_D_101: l1-dcache {
> - compatible = "arm,arch-cache";
> - };
> };
>
> CPU6: cpu@102 {
> @@ -241,12 +205,6 @@ CPU6: cpu@102 {
> capacity-dmips-mhz = <1536>;
> cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
> next-level-cache = <&L2_1>;
> - L1_I_102: l1-icache {
> - compatible = "arm,arch-cache";
> - };
> - L1_D_102: l1-dcache {
> - compatible = "arm,arch-cache";
> - };
> };
>
> CPU7: cpu@103 {
> @@ -257,12 +215,6 @@ CPU7: cpu@103 {
> capacity-dmips-mhz = <1536>;
> cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
> next-level-cache = <&L2_1>;
> - L1_I_103: l1-icache {
> - compatible = "arm,arch-cache";
> - };
> - L1_D_103: l1-dcache {
> - compatible = "arm,arch-cache";
> - };
> };
>
> cpu-map {
> --
> 2.32.0
>
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