linux-kernel - [PATCH 03/12] dt-bindings: riscv: add compatible strings for Nuclei UX600 series

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Thu, 27 Jan 2022 23:16:38 +0800
From:   Icenowy Zheng <icenowy@...leisys.com>
To:     Rob Herring <robh+dt@...nel.org>,
        Palmer Dabbelt <palmer@...belt.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Albert Ou <aou@...s.berkeley.edu>
Cc:     linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
        linux-riscv@...ts.infradead.org, linux-serial@...r.kernel.org,
        linux-spi@...r.kernel.org, Icenowy Zheng <icenowy@...leisys.com>
Subject: [PATCH 03/12] dt-bindings: riscv: add compatible strings for Nuclei UX600 series

Nuclei UX600 series are 64-bit, MMU-equipped CPUs, which can run Linux.

Add compatible strings for these CPU cores.

Signed-off-by: Icenowy Zheng <icenowy@...leisys.com>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index aa5fb64d57eb..f50f5c3dcc06 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -45,6 +45,13 @@ properties:
               - sifive,u54-mc
           - const: sifive,rocket0
           - const: riscv
+      - items:
+          - enum:
+              - nuclei,ux605
+              - nuclei,ux607
+              - nuclei,ux608
+          - const: nuclei,ux600
+          - const: riscv
       - const: riscv    # Simulator only
     description:
       Identifies that the hart uses the RISC-V instruction set
-- 
2.30.2