lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-Id: <20220130135634.1213301-2-guoren@kernel.org>
Date:   Sun, 30 Jan 2022 21:56:33 +0800
From:   guoren@...nel.org
To:     guoren@...nel.org, anup@...infault.org, maz@...nel.org,
        tglx@...utronix.de, palmer@...belt.com, samuel@...lland.org
Cc:     linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org,
        devicetree@...r.kernel.org, Guo Ren <guoren@...ux.alibaba.com>,
        Heiko Stuebner <heiko@...ech.de>,
        Rob Herring <robh@...nel.org>, Rob Herring <robh+dt@...nel.org>
Subject: [PATCH V7 1/2] dt-bindings: update riscv plic compatible string

From: Guo Ren <guoren@...ux.alibaba.com>

Add the compatible string "thead,c900-plic" to the riscv plic
bindings to support allwinner d1 SOC which contains c906 core.

Signed-off-by: Guo Ren <guoren@...ux.alibaba.com>
Cc: Anup Patel <anup@...infault.org>
Cc: Heiko Stuebner <heiko@...ech.de>
Cc: Rob Herring <robh@...nel.org>
Cc: Rob Herring <robh+dt@...nel.org>
Cc: Palmer Dabbelt <palmer@...belt.com>
Cc: Samuel Holland <samuel@...lland.org>
---
 .../sifive,plic-1.0.0.yaml                    | 21 +++++++++++++------
 1 file changed, 15 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 28b6b17fe4b2..1fa5aa7e4c2e 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -35,6 +35,10 @@ description:
   contains a specific memory layout, which is documented in chapter 8 of the
   SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
 
+  The thead,c900-plic is different from sifive,plic-1.0.0 in opensbi, the
+  T-HEAD PLIC implementation requires setting a delegation bit to allow access
+  from S-mode. So add thead,c900-plic to distinguish them.
+
 maintainers:
   - Sagar Kadam <sagar.kadam@...ive.com>
   - Paul Walmsley  <paul.walmsley@...ive.com>
@@ -42,12 +46,17 @@ maintainers:
 
 properties:
   compatible:
-    items:
-      - enum:
-          - sifive,fu540-c000-plic
-          - starfive,jh7100-plic
-          - canaan,k210-plic
-      - const: sifive,plic-1.0.0
+    oneOf:
+      - items:
+          - enum:
+              - sifive,fu540-c000-plic
+              - starfive,jh7100-plic
+              - canaan,k210-plic
+          - const: sifive,plic-1.0.0
+      - items:
+          - enum:
+              - allwinner,sun20i-d1-plic
+          - const: thead,c900-plic
 
   reg:
     maxItems: 1
-- 
2.25.1

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ