linux-kernel - [RFC PATCH 1/3] dt-bindings: clock: Add s32g2 clock binding

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20220207132444.3653-2-clin@suse.com>
Date:   Mon,  7 Feb 2022 21:24:42 +0800
From:   Chester Lin <clin@...e.com>
To:     Rob Herring <robh+dt@...nel.org>,
        Andreas Färber <afaerber@...e.de>,
        Matthias Brugger <mbrugger@...e.com>, s32@....com,
        Ghennadi Procopciuc <Ghennadi.Procopciuc@....com>
CC:     linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org,
        Radu Nicolae Pirea <radu-nicolae.pirea@....nxp.com>,
        "Ivan T . Ivanov" <iivanov@...e.de>,
        "Lee, Chun-Yi" <jlee@...e.com>, Chester Lin <clin@...e.com>
Subject: [RFC PATCH 1/3] dt-bindings: clock: Add s32g2 clock binding

Add clock binding for S32G based on SCMI Clock Management Protocol (0x14)

Signed-off-by: Chester Lin <clin@...e.com>
---
 include/dt-bindings/clock/s32g2-clock.h | 28 +++++++++++++++++++++++++
 1 file changed, 28 insertions(+)
 create mode 100644 include/dt-bindings/clock/s32g2-clock.h

diff --git a/include/dt-bindings/clock/s32g2-clock.h b/include/dt-bindings/clock/s32g2-clock.h
new file mode 100644
index 000000000000..6d8606293865
--- /dev/null
+++ b/include/dt-bindings/clock/s32g2-clock.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright 2020-2022 NXP
+ */
+#ifndef __DT_BINDINGS_SCMI_CLOCK_S32G2_H
+#define __DT_BINDINGS_SCMI_CLOCK_S32G2_H
+
+#define S32G2_SCMI_CLK_BASE_ID		0U
+#define S32G2_SCMI_CLK(N)		((N) + S32G2_SCMI_CLK_BASE_ID)
+
+/* GMAC0 - SGMII */
+#define S32G2_SCMI_CLK_GMAC0_RX_SGMII	S32G2_SCMI_CLK(16)
+#define S32G2_SCMI_CLK_GMAC0_TX_SGMII	S32G2_SCMI_CLK(17)
+/* GMAC0 - RGMII */
+#define S32G2_SCMI_CLK_GMAC0_RX_RGMII	S32G2_SCMI_CLK(19)
+#define S32G2_SCMI_CLK_GMAC0_TX_RGMII	S32G2_SCMI_CLK(20)
+/* GMAC0 - RMII */
+#define S32G2_SCMI_CLK_GMAC0_RX_RMII	S32G2_SCMI_CLK(22)
+#define S32G2_SCMI_CLK_GMAC0_TX_RMII	S32G2_SCMI_CLK(23)
+/* GMAC0 - MII */
+#define S32G2_SCMI_CLK_GMAC0_RX_MII	S32G2_SCMI_CLK(25)
+#define S32G2_SCMI_CLK_GMAC0_TX_MII	S32G2_SCMI_CLK(26)
+#define S32G2_SCMI_CLK_GMAC0_AXI	S32G2_SCMI_CLK(28)
+/* uSDHC */
+#define S32G2_SCMI_CLK_USDHC_AHB	S32G2_SCMI_CLK(35)
+#define S32G2_SCMI_CLK_USDHC_MODULE	S32G2_SCMI_CLK(36)
+#define S32G2_SCMI_CLK_USDHC_CORE	S32G2_SCMI_CLK(37)
+#endif
-- 
2.33.1