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Message-ID: <ae45a637-2c67-4126-3007-6829320d5659@huawei.com>
Date:   Tue, 8 Feb 2022 19:21:05 +0800
From:   Yicong Yang <yangyicong@...wei.com>
To:     John Garry <john.garry@...wei.com>,
        Yicong Yang <yangyicong@...ilicon.com>,
        "gregkh@...uxfoundation.org" <gregkh@...uxfoundation.org>,
        "helgaas@...nel.org" <helgaas@...nel.org>,
        "alexander.shishkin@...ux.intel.com" 
        <alexander.shishkin@...ux.intel.com>,
        "lorenzo.pieralisi@....com" <lorenzo.pieralisi@....com>,
        "will@...nel.org" <will@...nel.org>,
        "mark.rutland@....com" <mark.rutland@....com>,
        "mathieu.poirier@...aro.org" <mathieu.poirier@...aro.org>,
        "suzuki.poulose@....com" <suzuki.poulose@....com>,
        "mike.leach@...aro.org" <mike.leach@...aro.org>,
        "leo.yan@...aro.org" <leo.yan@...aro.org>,
        Jonathan Cameron <jonathan.cameron@...wei.com>,
        "daniel.thompson@...aro.org" <daniel.thompson@...aro.org>,
        "joro@...tes.org" <joro@...tes.org>,
        Shameerali Kolothum Thodi 
        <shameerali.kolothum.thodi@...wei.com>,
        "robin.murphy@....com" <robin.murphy@....com>,
        "peterz@...radead.org" <peterz@...radead.org>,
        "mingo@...hat.com" <mingo@...hat.com>,
        "acme@...nel.org" <acme@...nel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "coresight@...ts.linaro.org" <coresight@...ts.linaro.org>,
        "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
        "linux-perf-users@...r.kernel.org" <linux-perf-users@...r.kernel.org>,
        "iommu@...ts.linux-foundation.org" <iommu@...ts.linux-foundation.org>
CC:     "Zengtao (B)" <prime.zeng@...ilicon.com>,
        "liuqi (BA)" <liuqi115@...wei.com>,
        Zhangshaokun <zhangshaokun@...ilicon.com>,
        Linuxarm <linuxarm@...wei.com>,
        "Song Bao Hua (Barry Song)" <song.bao.hua@...ilicon.com>
Subject: Re: [PATCH v3 8/8] iommu/arm-smmu-v3: Make default domain type of
 HiSilicon PTT device to identity

On 2022/2/8 16:05, John Garry wrote:
> On 24/01/2022 13:11, Yicong Yang wrote:
>> The DMA of HiSilicon PTT device can only work with identical
>> mapping. So add a quirk for the device to force the domain
>> passthrough.
> 
> This patch should be earlier in the series, before the PTT driver, and the comment on hisi_ptt_check_iommu_mapping() should mention what is going on here.
> 

ok I'll reorder the serives and modify the comments of hisi_ptt_check_iommu_mapping() like:

/*
 * The DMA of PTT trace can only use direct mapping, due to some
 * hardware restriction. Check whether there is an iommu or the
 * policy of the iommu domain is passthrough, otherwise the trace
 * cannot work.
 *
 * The PTT device is supposed to behind the arm smmu v3, which
 * should have passthrough the device by a quirk. Otherwise user
 * should manually set the iommu domain type to identity through
 * sysfs.
 */

>>
>> Signed-off-by: Yicong Yang <yangyicong@...ilicon.com>
>> ---
>>   drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 16 ++++++++++++++++
>>   1 file changed, 16 insertions(+)
>>
>> diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
>> index 6dc6d8b6b368..6f67a2b1dd27 100644
>> --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
>> +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
>> @@ -2838,6 +2838,21 @@ static int arm_smmu_dev_disable_feature(struct device *dev,
>>       }
>>   }
>>   +#define IS_HISI_PTT_DEVICE(pdev)    ((pdev)->vendor == PCI_VENDOR_ID_HUAWEI && \
>> +                     (pdev)->device == 0xa12e)
> 
> I assume that not all revisions will require this check, right?
> 

For current revisions it's necessary.

>> +
>> +static int arm_smmu_def_domain_type(struct device *dev)
>> +{
>> +    if (dev_is_pci(dev)) {
>> +        struct pci_dev *pdev = to_pci_dev(dev);
>> +
>> +        if (IS_HISI_PTT_DEVICE(pdev))
>> +            return IOMMU_DOMAIN_IDENTITY;
>> +    }
>> +
>> +    return 0;
>> +}
>> +
>>   static struct iommu_ops arm_smmu_ops = {
>>       .capable        = arm_smmu_capable,
>>       .domain_alloc        = arm_smmu_domain_alloc,
>> @@ -2863,6 +2878,7 @@ static struct iommu_ops arm_smmu_ops = {
>>       .sva_unbind        = arm_smmu_sva_unbind,
>>       .sva_get_pasid        = arm_smmu_sva_get_pasid,
>>       .page_response        = arm_smmu_page_response,
>> +    .def_domain_type    = arm_smmu_def_domain_type,
>>       .pgsize_bitmap        = -1UL, /* Restricted during device attach */
>>       .owner            = THIS_MODULE,
>>   };
> 
> .

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