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Message-ID: <CAMuHMdX4P82B96ZbANyF6cWo9CnrW9hg5up6pCb0PZ99=sPZ_A@mail.gmail.com>
Date: Fri, 11 Feb 2022 13:52:17 +0100
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Andreas Schwab <schwab@...ux-m68k.org>
Cc: Atish Patra <atishp@...osinc.com>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
Albert Ou <aou@...s.berkeley.edu>,
Atish Patra <atishp@...shpatra.org>,
Anup Patel <anup@...infault.org>,
Damien Le Moal <damien.lemoal@....com>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@...r.kernel.org>, Jisheng Zhang <jszhang@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>,
linux-riscv <linux-riscv@...ts.infradead.org>,
Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Rob Herring <robh+dt@...nel.org>
Subject: Re: [PATCH v2 5/6] RISC-V: Do no continue isa string parsing without
correct XLEN
Hi Andreas,
On Thu, Feb 10, 2022 at 11:00 PM Andreas Schwab <schwab@...ux-m68k.org> wrote:
> On Feb 10 2022, Atish Patra wrote:
> > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > index 469b9739faf7..cca579bae8a0 100644
> > --- a/arch/riscv/kernel/cpufeature.c
> > +++ b/arch/riscv/kernel/cpufeature.c
> > @@ -84,6 +84,7 @@ void __init riscv_fill_hwcap(void)
> > for_each_of_cpu_node(node) {
> > unsigned long this_hwcap = 0;
> > uint64_t this_isa = 0;
> > + char *temp;
> >
> > if (riscv_of_processor_hartid(node) < 0)
> > continue;
> > @@ -93,6 +94,7 @@ void __init riscv_fill_hwcap(void)
> > continue;
> > }
> >
> > + temp = (char *)isa;
>
> There should be no need for this cast.
Indeed, but only if "temp" is changed to "const char *".
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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