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Message-ID: <877da2xu32.fsf@igel.home>
Date: Thu, 10 Feb 2022 22:58:09 +0100
From: Andreas Schwab <schwab@...ux-m68k.org>
To: Atish Patra <atishp@...osinc.com>
Cc: linux-kernel@...r.kernel.org, Albert Ou <aou@...s.berkeley.edu>,
Atish Patra <atishp@...shpatra.org>,
Anup Patel <anup@...infault.org>,
Damien Le Moal <damien.lemoal@....com>,
devicetree@...r.kernel.org, Jisheng Zhang <jszhang@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>,
linux-riscv@...ts.infradead.org,
Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Rob Herring <robh+dt@...nel.org>
Subject: Re: [PATCH v2 5/6] RISC-V: Do no continue isa string parsing
without correct XLEN
On Feb 10 2022, Atish Patra wrote:
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 469b9739faf7..cca579bae8a0 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -84,6 +84,7 @@ void __init riscv_fill_hwcap(void)
> for_each_of_cpu_node(node) {
> unsigned long this_hwcap = 0;
> uint64_t this_isa = 0;
> + char *temp;
>
> if (riscv_of_processor_hartid(node) < 0)
> continue;
> @@ -93,6 +94,7 @@ void __init riscv_fill_hwcap(void)
> continue;
> }
>
> + temp = (char *)isa;
There should be no need for this cast.
--
Andreas Schwab, schwab@...ux-m68k.org
GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510 2552 DF73 E780 A9DA AEC1
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